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authorTomeu Vizoso <tomeu@tomeuvizoso.net>2023-11-21 07:32:59 +0100
committerLucas Stach <l.stach@pengutronix.de>2024-01-23 10:20:21 +0100
commit1dccdba084897443d116508a8ed71e0ac8a031a4 (patch)
treeea487b26cee877ce4ad1d5ff97caab563eef47b0 /include/uapi/drm
parentb0da08559c749ddc0e9a6e378b292ffa6845fb01 (diff)
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drm/etnaviv: Expose a few more chipspecs to userspace
These ones will be needed to make use fo the NN and TP units in the NPUs based on Vivante IP. Also fix the number of NN cores in the VIPNano-qi. Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Acked-by: Christian Gmeiner <cgmeiner@igalia.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'include/uapi/drm')
-rw-r--r--include/uapi/drm/etnaviv_drm.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/uapi/drm/etnaviv_drm.h b/include/uapi/drm/etnaviv_drm.h
index af024d90453d..d87410a8443a 100644
--- a/include/uapi/drm/etnaviv_drm.h
+++ b/include/uapi/drm/etnaviv_drm.h
@@ -77,6 +77,11 @@ struct drm_etnaviv_timespec {
#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
+#define ETNAVIV_PARAM_GPU_NN_CORE_COUNT 0x1f
+#define ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE 0x20
+#define ETNAVIV_PARAM_GPU_TP_CORE_COUNT 0x21
+#define ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE 0x22
+#define ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE 0x23
#define ETNA_MAX_PIPES 4