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authorPeter De Schrijver <pdeschrijver@nvidia.com>2017-02-28 16:37:22 +0200
committerThierry Reding <treding@nvidia.com>2017-03-20 14:07:48 +0100
commit24c3ebef1ab6d5620eaaa51f69223118cac97db6 (patch)
treecbeb8fe67d558a7e2986caee5089c4691e6d65af /include
parente827ba1840bc6a9540deb81c6df6943a19e0e891 (diff)
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clk: tegra: Add aclk
This clock clocks the ADSP Cortex-A9. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/tegra210-car.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 5aa10278ea1b..8744b19cca3e 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -396,6 +396,8 @@
#define TEGRA210_CLK_PLL_C_UD 364
#define TEGRA210_CLK_SCLK_MUX 365
+#define TEGRA210_CLK_ACLK 370
+
#define TEGRA210_CLK_DMIC1_SYNC_CLK 388
#define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389
#define TEGRA210_CLK_DMIC2_SYNC_CLK 390