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| author | Roger Quadros <rogerq@ti.com> | 2015-07-30 14:49:23 +0300 |
|---|---|---|
| committer | Roger Quadros <rogerq@ti.com> | 2016-04-15 11:52:28 +0300 |
| commit | 384258f252727c67772bbd48dad3185a30ba50d3 (patch) | |
| tree | dd753eb5c2977384b4885878394f4bc0946d95f1 /include | |
| parent | 512d73d1c64f15da9cdcdcdfba3cd8db0d4d94cc (diff) | |
| download | linux-stable-384258f252727c67772bbd48dad3185a30ba50d3.tar.gz linux-stable-384258f252727c67772bbd48dad3185a30ba50d3.tar.bz2 linux-stable-384258f252727c67772bbd48dad3185a30ba50d3.zip | |
memory: omap-gpmc: Implement IRQ domain for NAND IRQs
GPMC provides 2 interrupts for NAND use. i.e. fifoevent and termcount.
Use IRQ domain for this. NAND device tree node can then
get the necessary interrupts by using gpmc as the interrupt parent.
Legacy boot uses gpmc_get_client_irq to get the
NAND interrupts from the GPMC IRQ domain.
Get rid of custom bitmasks and use IRQ domain for that
as well.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/omap-gpmc.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h index dc2ada6fb9b4..9e9d79e8efa5 100644 --- a/include/linux/omap-gpmc.h +++ b/include/linux/omap-gpmc.h @@ -11,8 +11,9 @@ #define GPMC_CONFIG_WP 0x00000005 -#define GPMC_IRQ_FIFOEVENTENABLE 0x01 -#define GPMC_IRQ_COUNT_EVENT 0x02 +/* IRQ numbers in GPMC IRQ domain for legacy boot use */ +#define GPMC_IRQ_FIFOEVENTENABLE 0 +#define GPMC_IRQ_COUNT_EVENT 1 /** * gpmc_nand_ops - Interface between NAND and GPMC |