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| author | Asutosh Das <quic_asutoshd@quicinc.com> | 2023-01-13 12:48:44 -0800 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2023-01-13 21:03:37 -0500 |
| commit | 4682abfae2eb3a1c138130cfd6d71411d81aaa00 (patch) | |
| tree | 11e165aa78c758c281395c79e04e645f2f60bdbf /include | |
| parent | 7224c806876e46cfaf46b1c90da8d5c2e1f2108f (diff) | |
| download | linux-stable-4682abfae2eb3a1c138130cfd6d71411d81aaa00.tar.gz linux-stable-4682abfae2eb3a1c138130cfd6d71411d81aaa00.tar.bz2 linux-stable-4682abfae2eb3a1c138130cfd6d71411d81aaa00.zip | |
scsi: ufs: core: mcq: Allocate memory for MCQ mode
To read the bqueuedepth, the device descriptor is fetched in Single
Doorbell Mode. This allocated memory may not be enough for MCQ mode because
the number of tags supported in MCQ mode may be larger than in SDB mode.
Hence, release the memory allocated in SDB mode and allocate memory for MCQ
mode operation. Define the UFS hardware queue and Completion Queue Entry.
Co-developed-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Asutosh Das <quic_asutoshd@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/ufs/ufshcd.h | 20 | ||||
| -rw-r--r-- | include/ufs/ufshci.h | 22 |
2 files changed, 42 insertions, 0 deletions
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 57854bb0395e..311113c8e92d 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -876,6 +876,8 @@ enum ufshcd_res { * @mcq_sup: is mcq supported by UFSHC * @res: array of resource info of MCQ registers * @mcq_base: Multi circular queue registers base address + * @uhq: array of supported hardware queues + * @dev_cmd_queue: Queue for issuing device management commands */ struct ufs_hba { void __iomem *mmio_base; @@ -1034,6 +1036,24 @@ struct ufs_hba { bool mcq_sup; struct ufshcd_res_info res[RES_MAX]; void __iomem *mcq_base; + struct ufs_hw_queue *uhq; + struct ufs_hw_queue *dev_cmd_queue; +}; + +/** + * struct ufs_hw_queue - per hardware queue structure + * @sqe_base_addr: submission queue entry base address + * @sqe_dma_addr: submission queue dma address + * @cqe_base_addr: completion queue base address + * @cqe_dma_addr: completion queue dma address + * @max_entries: max number of slots in this hardware queue + */ +struct ufs_hw_queue { + void *sqe_base_addr; + dma_addr_t sqe_dma_addr; + struct cq_entry *cqe_base_addr; + dma_addr_t cqe_dma_addr; + u32 max_entries; }; #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h index 845a82a57f65..0d621e9e3146 100644 --- a/include/ufs/ufshci.h +++ b/include/ufs/ufshci.h @@ -492,6 +492,28 @@ struct utp_transfer_req_desc { __le16 prd_table_offset; }; +/* MCQ Completion Queue Entry */ +struct cq_entry { + /* DW 0-1 */ + __le64 command_desc_base_addr; + + /* DW 2 */ + __le16 response_upiu_length; + __le16 response_upiu_offset; + + /* DW 3 */ + __le16 prd_table_length; + __le16 prd_table_offset; + + /* DW 4 */ + __le32 status; + + /* DW 5-7 */ + __le32 reserved[3]; +}; + +static_assert(sizeof(struct cq_entry) == 32); + /* * UTMRD structure. */ |