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| author | Jyri Sarha <jyri.sarha@intel.com> | 2023-03-21 11:26:53 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-03-21 12:13:30 +0000 |
| commit | cb3cdef33136baceada86ba2a21ba30cd53a9087 (patch) | |
| tree | f5f4441a7af256798066b7c4cf979c9d17b85ea0 /include | |
| parent | 3d3e223f09ed59f7a47d27cf4301b4d0d5c7fc3d (diff) | |
| download | linux-stable-cb3cdef33136baceada86ba2a21ba30cd53a9087.tar.gz linux-stable-cb3cdef33136baceada86ba2a21ba30cd53a9087.tar.bz2 linux-stable-cb3cdef33136baceada86ba2a21ba30cd53a9087.zip | |
ASoC: SOF: ipc4: Add macros for chain-dma message bits
In the chained DMA mode, the firmware allocates buffers for the host
and link DMA, and takes care of copying data between host- and
link-DMA buffers in a low-latency thread. This is different to a
regular pipeline, no processing is allowed, and the connection between
host- and link DMA is handled with a dedicated IPC.
This patch exposes the macros needed to create the required IPC messages.
Signed-off-by: Jyri Sarha <jyri.sarha@intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20230321092654.7292-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sound/sof/ipc4/header.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/include/sound/sof/ipc4/header.h b/include/sound/sof/ipc4/header.h index 49ff1558a171..78568abe2673 100644 --- a/include/sound/sof/ipc4/header.h +++ b/include/sound/sof/ipc4/header.h @@ -196,6 +196,35 @@ enum sof_ipc4_pipeline_state { #define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT 16 #define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID(x) ((x) << SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT) +/* chain dma ipc message */ +#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT 0 +#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK GENMASK(4, 0) +#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT) & \ + SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK) + +#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT 8 +#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK GENMASK(12, 8) +#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT) & \ + SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK) + +#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT 16 +#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK BIT(16) +#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT) + +#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT 17 +#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK BIT(17) +#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT) + +#define SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT 18 +#define SOF_IPC4_GLB_CHAIN_DMA_SCS_MASK BIT(18) +#define SOF_IPC4_GLB_CHAIN_DMA_SCS(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT) + +#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT 0 +#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK GENMASK(24, 0) +#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE(x) (((x) << \ + SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT) & \ + SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK) + enum sof_ipc4_channel_config { /* one channel only. */ SOF_IPC4_CHANNEL_CONFIG_MONO, |