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authorArnd Bergmann <arnd@arndb.de>2017-03-02 17:52:44 +0100
committerArnd Bergmann <arnd@arndb.de>2017-03-02 17:52:44 +0100
commitd4b80d9aacfa760cf0f363caec33b6d54f3afa2b (patch)
treecbc1f1dc0d41e77dfef8f11d8cd1a2f8efdab624 /include
parentb2e3c4319d40c9055c3c587cdb82ba69b50e919d (diff)
parent3e011039a3f376f246e662b0e3ffb08018e3416e (diff)
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Merge branch 'next/late' with mainline
* next/late: (25 commits) arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ARM64: dts: meson-gxbb-vega-s95: Add LED ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/exynos5433.h5
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h6
-rw-r--r--include/dt-bindings/pinctrl/samsung.h8
3 files changed, 18 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 4fa6bb2136e3..be39d23e6a32 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -771,7 +771,10 @@
#define CLK_PCLK_DECON 113
-#define DISP_NR_CLK 114
+#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114
+#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115
+
+#define DISP_NR_CLK 116
/* CMU_AUD */
#define CLK_MOUT_AUD_PLL_USER 1
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index baade6f429d0..692846c7941b 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -14,15 +14,21 @@
#define CLKID_MPLL2 15
#define CLKID_SPI 34
#define CLKID_I2C 22
+#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
+#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_SANA 69
+#define CLKID_GCLK_VENCI_INT0 77
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
+#define CLKID_SAR_ADC_CLK 97
+#define CLKID_SAR_ADC_SEL 98
#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h
index e0ebb20ffdd3..b7aa3646208b 100644
--- a/include/dt-bindings/pinctrl/samsung.h
+++ b/include/dt-bindings/pinctrl/samsung.h
@@ -68,4 +68,12 @@
#define EXYNOS_PIN_FUNC_6 6
#define EXYNOS_PIN_FUNC_F 0xf
+/* Drive strengths for Exynos7 FSYS1 block */
+#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
+#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
+#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
+#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
+#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
+#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
+
#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */