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author | Linus Torvalds <torvalds@linux-foundation.org> | 2021-11-03 07:49:25 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2021-11-03 07:49:25 -0700 |
commit | ff0700f03609b9f0defacd4ce96d9519d721e0a2 (patch) | |
tree | 4b7ac6cf015e39f82ef0706ce465a224a43dac42 /include | |
parent | dcd68326d29b62f3039e4f4d23d3e38f24d37360 (diff) | |
parent | df0380b9539b04c1ae8854a984098da06d5f1e67 (diff) | |
download | linux-stable-ff0700f03609b9f0defacd4ce96d9519d721e0a2.tar.gz linux-stable-ff0700f03609b9f0defacd4ce96d9519d721e0a2.tar.bz2 linux-stable-ff0700f03609b9f0defacd4ce96d9519d721e0a2.zip |
Merge tag 'sound-5.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
Pull sound updates from Takashi Iwai:
"Lots of code development have been see in ASoC side as usual, while
the continued development on memalloc helper and USB-audio low-
latency support are found in the rest.
Note that a few changes in the unusual places like arch/sh are
included, which are a part of ASoC DAI format cleanups.
ALSA core:
- Continued memalloc helper updates and cleanups, now supporting
non-coherent and non-contiguous pages
- Fixes for races in mixer OSS layer
ASoC:
- A new version of the audio graph card which supports a wider range
of systems
- Several conversions to YAML DT bindings
- Continuing cleanups to the SOF and Intel code
- Move of the Cirrus DSP framework into drivers/firmware to allow for
future use by non-audio DSPs
- An overhaul of the cs42l42 driver, correcting many problems
- DAI format terminology conversions over many drivers for cleanups
- Support for AMD Vangogh and Yelow Cap, Cirrus CS35L41, Maxim
MAX98520 and MAX98360A, Mediatek MT8195, Nuvoton NAU8821, nVidia
Tegra210, NXP i.MX8ULP, Qualcomm AudioReach, Realtek ALC5682I-VS,
RT5682S, and RT9120 and Rockchip RV1126 and RK3568
USB-audio:
- Continued improvements on low-latency playback
- Quirks for Pioneer devices, Line6 HX-Stomp XL, Audient iD14
HD-audio:
- Reduce excessive udelay() calls on Intel platforms; this should
reduce the CPU load with PulseAudio
- Quirks for HP and Clevo laptops
FireWire:
- Support for meter information on MOTU"
* tag 'sound-5.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (513 commits)
ALSA: usb-audio: Add quirk for Audient iD14
ALSA: hda/realtek: Add quirk for Clevo PC70HS
ALSA: usb-audio: Line6 HX-Stomp XL USB_ID for 48k-fixed quirk
ALSA: usb-audio: Add registration quirk for JBL Quantum 400
ASoC: rsnd: Fix an error handling path in 'rsnd_node_count()'
ASoC: tlv320aic3x: Make aic3x_remove() return void
ASoC: Intel: soc-acpi: use const for all uses of snd_soc_acpi_codecs
ASoC: Intel: soc-acpi-cht: shrink tables using compatible IDs
ASoC: Intel: soc-acpi-byt: shrink tables using compatible IDs
ASoC: Intel: sof_rt5682: use comp_ids to enumerate rt5682s
ASoC: Intel: sof_rt5682: detect codec variant in probe function
ASoC: soc-acpi: add comp_ids field for machine driver matching
ASoC: mediatek: mt8195: add mt8195-mt6359-rt1011-rt5682 bindings document
ASoC: mediatek: mt8195: add machine driver with mt6359, rt1011 and rt5682
ASoC: Stop dummy from overriding hwparams
ASoC: topology: Change topology device to card device
ASoC: topology: Use correct device for prints
ASoC: topology: Check for dapm widget completeness
ASoC: topology: Add header payload_size verification
ASoC: core: Remove invalid snd_soc_component_set_jack call
...
Diffstat (limited to 'include')
24 files changed, 1321 insertions, 233 deletions
diff --git a/include/dt-bindings/soc/qcom,gpr.h b/include/dt-bindings/soc/qcom,gpr.h new file mode 100644 index 000000000000..3107da59319c --- /dev/null +++ b/include/dt-bindings/soc/qcom,gpr.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef __DT_BINDINGS_QCOM_GPR_H +#define __DT_BINDINGS_QCOM_GPR_H + +/* DOMAINS */ + +#define GPR_DOMAIN_ID_MODEM 1 +#define GPR_DOMAIN_ID_ADSP 2 +#define GPR_DOMAIN_ID_APPS 3 + +/* Static Services */ + +#define GPR_APM_MODULE_IID 1 +#define GPR_PRM_MODULE_IID 2 +#define GPR_AMDB_MODULE_IID 3 +#define GPR_VCPM_MODULE_IID 4 + +#endif /* __DT_BINDINGS_QCOM_GPR_H */ diff --git a/include/dt-bindings/sound/qcom,lpass.h b/include/dt-bindings/sound/qcom,lpass.h index 7b0b80b38699..a9404c3b8884 100644 --- a/include/dt-bindings/sound/qcom,lpass.h +++ b/include/dt-bindings/sound/qcom,lpass.h @@ -10,6 +10,37 @@ #define LPASS_DP_RX 5 +#define LPASS_CDC_DMA_RX0 6 +#define LPASS_CDC_DMA_RX1 7 +#define LPASS_CDC_DMA_RX2 8 +#define LPASS_CDC_DMA_RX3 9 +#define LPASS_CDC_DMA_RX4 10 +#define LPASS_CDC_DMA_RX5 11 +#define LPASS_CDC_DMA_RX6 12 +#define LPASS_CDC_DMA_RX7 13 +#define LPASS_CDC_DMA_RX8 14 +#define LPASS_CDC_DMA_RX9 15 + +#define LPASS_CDC_DMA_TX0 16 +#define LPASS_CDC_DMA_TX1 17 +#define LPASS_CDC_DMA_TX2 18 +#define LPASS_CDC_DMA_TX3 19 +#define LPASS_CDC_DMA_TX4 20 +#define LPASS_CDC_DMA_TX5 21 +#define LPASS_CDC_DMA_TX6 22 +#define LPASS_CDC_DMA_TX7 23 +#define LPASS_CDC_DMA_TX8 24 + +#define LPASS_CDC_DMA_VA_TX0 25 +#define LPASS_CDC_DMA_VA_TX1 26 +#define LPASS_CDC_DMA_VA_TX2 27 +#define LPASS_CDC_DMA_VA_TX3 28 +#define LPASS_CDC_DMA_VA_TX4 29 +#define LPASS_CDC_DMA_VA_TX5 30 +#define LPASS_CDC_DMA_VA_TX6 31 +#define LPASS_CDC_DMA_VA_TX7 32 +#define LPASS_CDC_DMA_VA_TX8 33 + #define LPASS_MCLK0 0 #endif /* __DT_QCOM_LPASS_H */ diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h index 66c21ab03eef..9d5d89cfabcf 100644 --- a/include/dt-bindings/sound/qcom,q6afe.h +++ b/include/dt-bindings/sound/qcom,q6afe.h @@ -2,207 +2,8 @@ #ifndef __DT_BINDINGS_Q6_AFE_H__ #define __DT_BINDINGS_Q6_AFE_H__ -/* Audio Front End (AFE) virtual ports IDs */ -#define HDMI_RX 1 -#define SLIMBUS_0_RX 2 -#define SLIMBUS_0_TX 3 -#define SLIMBUS_1_RX 4 -#define SLIMBUS_1_TX 5 -#define SLIMBUS_2_RX 6 -#define SLIMBUS_2_TX 7 -#define SLIMBUS_3_RX 8 -#define SLIMBUS_3_TX 9 -#define SLIMBUS_4_RX 10 -#define SLIMBUS_4_TX 11 -#define SLIMBUS_5_RX 12 -#define SLIMBUS_5_TX 13 -#define SLIMBUS_6_RX 14 -#define SLIMBUS_6_TX 15 -#define PRIMARY_MI2S_RX 16 -#define PRIMARY_MI2S_TX 17 -#define SECONDARY_MI2S_RX 18 -#define SECONDARY_MI2S_TX 19 -#define TERTIARY_MI2S_RX 20 -#define TERTIARY_MI2S_TX 21 -#define QUATERNARY_MI2S_RX 22 -#define QUATERNARY_MI2S_TX 23 -#define PRIMARY_TDM_RX_0 24 -#define PRIMARY_TDM_TX_0 25 -#define PRIMARY_TDM_RX_1 26 -#define PRIMARY_TDM_TX_1 27 -#define PRIMARY_TDM_RX_2 28 -#define PRIMARY_TDM_TX_2 29 -#define PRIMARY_TDM_RX_3 30 -#define PRIMARY_TDM_TX_3 31 -#define PRIMARY_TDM_RX_4 32 -#define PRIMARY_TDM_TX_4 33 -#define PRIMARY_TDM_RX_5 34 -#define PRIMARY_TDM_TX_5 35 -#define PRIMARY_TDM_RX_6 36 -#define PRIMARY_TDM_TX_6 37 -#define PRIMARY_TDM_RX_7 38 -#define PRIMARY_TDM_TX_7 39 -#define SECONDARY_TDM_RX_0 40 -#define SECONDARY_TDM_TX_0 41 -#define SECONDARY_TDM_RX_1 42 -#define SECONDARY_TDM_TX_1 43 -#define SECONDARY_TDM_RX_2 44 -#define SECONDARY_TDM_TX_2 45 -#define SECONDARY_TDM_RX_3 46 -#define SECONDARY_TDM_TX_3 47 -#define SECONDARY_TDM_RX_4 48 -#define SECONDARY_TDM_TX_4 49 -#define SECONDARY_TDM_RX_5 50 -#define SECONDARY_TDM_TX_5 51 -#define SECONDARY_TDM_RX_6 52 -#define SECONDARY_TDM_TX_6 53 -#define SECONDARY_TDM_RX_7 54 -#define SECONDARY_TDM_TX_7 55 -#define TERTIARY_TDM_RX_0 56 -#define TERTIARY_TDM_TX_0 57 -#define TERTIARY_TDM_RX_1 58 -#define TERTIARY_TDM_TX_1 59 -#define TERTIARY_TDM_RX_2 60 -#define TERTIARY_TDM_TX_2 61 -#define TERTIARY_TDM_RX_3 62 -#define TERTIARY_TDM_TX_3 63 -#define TERTIARY_TDM_RX_4 64 -#define TERTIARY_TDM_TX_4 65 -#define TERTIARY_TDM_RX_5 66 -#define TERTIARY_TDM_TX_5 67 -#define TERTIARY_TDM_RX_6 68 -#define TERTIARY_TDM_TX_6 69 -#define TERTIARY_TDM_RX_7 70 -#define TERTIARY_TDM_TX_7 71 -#define QUATERNARY_TDM_RX_0 72 -#define QUATERNARY_TDM_TX_0 73 -#define QUATERNARY_TDM_RX_1 74 -#define QUATERNARY_TDM_TX_1 75 -#define QUATERNARY_TDM_RX_2 76 -#define QUATERNARY_TDM_TX_2 77 -#define QUATERNARY_TDM_RX_3 78 -#define QUATERNARY_TDM_TX_3 79 -#define QUATERNARY_TDM_RX_4 80 -#define QUATERNARY_TDM_TX_4 81 -#define QUATERNARY_TDM_RX_5 82 -#define QUATERNARY_TDM_TX_5 83 -#define QUATERNARY_TDM_RX_6 84 -#define QUATERNARY_TDM_TX_6 85 -#define QUATERNARY_TDM_RX_7 86 -#define QUATERNARY_TDM_TX_7 87 -#define QUINARY_TDM_RX_0 88 -#define QUINARY_TDM_TX_0 89 -#define QUINARY_TDM_RX_1 90 -#define QUINARY_TDM_TX_1 91 -#define QUINARY_TDM_RX_2 92 -#define QUINARY_TDM_TX_2 93 -#define QUINARY_TDM_RX_3 94 -#define QUINARY_TDM_TX_3 95 -#define QUINARY_TDM_RX_4 96 -#define QUINARY_TDM_TX_4 97 -#define QUINARY_TDM_RX_5 98 -#define QUINARY_TDM_TX_5 99 -#define QUINARY_TDM_RX_6 100 -#define QUINARY_TDM_TX_6 101 -#define QUINARY_TDM_RX_7 102 -#define QUINARY_TDM_TX_7 103 -#define DISPLAY_PORT_RX 104 -#define WSA_CODEC_DMA_RX_0 105 -#define WSA_CODEC_DMA_TX_0 106 -#define WSA_CODEC_DMA_RX_1 107 -#define WSA_CODEC_DMA_TX_1 108 -#define WSA_CODEC_DMA_TX_2 109 -#define VA_CODEC_DMA_TX_0 110 -#define VA_CODEC_DMA_TX_1 111 -#define VA_CODEC_DMA_TX_2 112 -#define RX_CODEC_DMA_RX_0 113 -#define TX_CODEC_DMA_TX_0 114 -#define RX_CODEC_DMA_RX_1 115 -#define TX_CODEC_DMA_TX_1 116 -#define RX_CODEC_DMA_RX_2 117 -#define TX_CODEC_DMA_TX_2 118 -#define RX_CODEC_DMA_RX_3 119 -#define TX_CODEC_DMA_TX_3 120 -#define RX_CODEC_DMA_RX_4 121 -#define TX_CODEC_DMA_TX_4 122 -#define RX_CODEC_DMA_RX_5 123 -#define TX_CODEC_DMA_TX_5 124 -#define RX_CODEC_DMA_RX_6 125 -#define RX_CODEC_DMA_RX_7 126 -#define QUINARY_MI2S_RX 127 -#define QUINARY_MI2S_TX 128 +/* This file exists due to backward compatibility reasons, Please do not DELETE! */ -#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 -#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 -#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 -#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 -#define LPASS_CLK_ID_TER_MI2S_IBIT 5 -#define LPASS_CLK_ID_TER_MI2S_EBIT 6 -#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 -#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 -#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 -#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 -#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 -#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 -#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 -#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 -#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 -#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 -#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 -#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 -#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 -#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 -#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 -#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 -#define LPASS_CLK_ID_QUI_MI2S_OSR 23 -#define LPASS_CLK_ID_PRI_PCM_IBIT 24 -#define LPASS_CLK_ID_PRI_PCM_EBIT 25 -#define LPASS_CLK_ID_SEC_PCM_IBIT 26 -#define LPASS_CLK_ID_SEC_PCM_EBIT 27 -#define LPASS_CLK_ID_TER_PCM_IBIT 28 -#define LPASS_CLK_ID_TER_PCM_EBIT 29 -#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 -#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 -#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 -#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 -#define LPASS_CLK_ID_QUI_PCM_OSR 34 -#define LPASS_CLK_ID_PRI_TDM_IBIT 35 -#define LPASS_CLK_ID_PRI_TDM_EBIT 36 -#define LPASS_CLK_ID_SEC_TDM_IBIT 37 -#define LPASS_CLK_ID_SEC_TDM_EBIT 38 -#define LPASS_CLK_ID_TER_TDM_IBIT 39 -#define LPASS_CLK_ID_TER_TDM_EBIT 40 -#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 -#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 -#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 -#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 -#define LPASS_CLK_ID_QUIN_TDM_OSR 45 -#define LPASS_CLK_ID_MCLK_1 46 -#define LPASS_CLK_ID_MCLK_2 47 -#define LPASS_CLK_ID_MCLK_3 48 -#define LPASS_CLK_ID_MCLK_4 49 -#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 -#define LPASS_CLK_ID_INT_MCLK_0 51 -#define LPASS_CLK_ID_INT_MCLK_1 52 -#define LPASS_CLK_ID_MCLK_5 53 -#define LPASS_CLK_ID_WSA_CORE_MCLK 54 -#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 -#define LPASS_CLK_ID_VA_CORE_MCLK 56 -#define LPASS_CLK_ID_TX_CORE_MCLK 57 -#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 -#define LPASS_CLK_ID_RX_CORE_MCLK 59 -#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 -#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 - -#define LPASS_HW_AVTIMER_VOTE 101 -#define LPASS_HW_MACRO_VOTE 102 -#define LPASS_HW_DCODEC_VOTE 103 - -#define Q6AFE_MAX_CLK_ID 104 - -#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 -#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> #endif /* __DT_BINDINGS_Q6_AFE_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h new file mode 100644 index 000000000000..0d3276c8fc11 --- /dev/null +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__ +#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__ + +/* LPASS Audio virtual ports IDs */ +#define HDMI_RX 1 +#define SLIMBUS_0_RX 2 +#define SLIMBUS_0_TX 3 +#define SLIMBUS_1_RX 4 +#define SLIMBUS_1_TX 5 +#define SLIMBUS_2_RX 6 +#define SLIMBUS_2_TX 7 +#define SLIMBUS_3_RX 8 +#define SLIMBUS_3_TX 9 +#define SLIMBUS_4_RX 10 +#define SLIMBUS_4_TX 11 +#define SLIMBUS_5_RX 12 +#define SLIMBUS_5_TX 13 +#define SLIMBUS_6_RX 14 +#define SLIMBUS_6_TX 15 +#define PRIMARY_MI2S_RX 16 +#define PRIMARY_MI2S_TX 17 +#define SECONDARY_MI2S_RX 18 +#define SECONDARY_MI2S_TX 19 +#define TERTIARY_MI2S_RX 20 +#define TERTIARY_MI2S_TX 21 +#define QUATERNARY_MI2S_RX 22 +#define QUATERNARY_MI2S_TX 23 +#define PRIMARY_TDM_RX_0 24 +#define PRIMARY_TDM_TX_0 25 +#define PRIMARY_TDM_RX_1 26 +#define PRIMARY_TDM_TX_1 27 +#define PRIMARY_TDM_RX_2 28 +#define PRIMARY_TDM_TX_2 29 +#define PRIMARY_TDM_RX_3 30 +#define PRIMARY_TDM_TX_3 31 +#define PRIMARY_TDM_RX_4 32 +#define PRIMARY_TDM_TX_4 33 +#define PRIMARY_TDM_RX_5 34 +#define PRIMARY_TDM_TX_5 35 +#define PRIMARY_TDM_RX_6 36 +#define PRIMARY_TDM_TX_6 37 +#define PRIMARY_TDM_RX_7 38 +#define PRIMARY_TDM_TX_7 39 +#define SECONDARY_TDM_RX_0 40 +#define SECONDARY_TDM_TX_0 41 +#define SECONDARY_TDM_RX_1 42 +#define SECONDARY_TDM_TX_1 43 +#define SECONDARY_TDM_RX_2 44 +#define SECONDARY_TDM_TX_2 45 +#define SECONDARY_TDM_RX_3 46 +#define SECONDARY_TDM_TX_3 47 +#define SECONDARY_TDM_RX_4 48 +#define SECONDARY_TDM_TX_4 49 +#define SECONDARY_TDM_RX_5 50 +#define SECONDARY_TDM_TX_5 51 +#define SECONDARY_TDM_RX_6 52 +#define SECONDARY_TDM_TX_6 53 +#define SECONDARY_TDM_RX_7 54 +#define SECONDARY_TDM_TX_7 55 +#define TERTIARY_TDM_RX_0 56 +#define TERTIARY_TDM_TX_0 57 +#define TERTIARY_TDM_RX_1 58 +#define TERTIARY_TDM_TX_1 59 +#define TERTIARY_TDM_RX_2 60 +#define TERTIARY_TDM_TX_2 61 +#define TERTIARY_TDM_RX_3 62 +#define TERTIARY_TDM_TX_3 63 +#define TERTIARY_TDM_RX_4 64 +#define TERTIARY_TDM_TX_4 65 +#define TERTIARY_TDM_RX_5 66 +#define TERTIARY_TDM_TX_5 67 +#define TERTIARY_TDM_RX_6 68 +#define TERTIARY_TDM_TX_6 69 +#define TERTIARY_TDM_RX_7 70 +#define TERTIARY_TDM_TX_7 71 +#define QUATERNARY_TDM_RX_0 72 +#define QUATERNARY_TDM_TX_0 73 +#define QUATERNARY_TDM_RX_1 74 +#define QUATERNARY_TDM_TX_1 75 +#define QUATERNARY_TDM_RX_2 76 +#define QUATERNARY_TDM_TX_2 77 +#define QUATERNARY_TDM_RX_3 78 +#define QUATERNARY_TDM_TX_3 79 +#define QUATERNARY_TDM_RX_4 80 +#define QUATERNARY_TDM_TX_4 81 +#define QUATERNARY_TDM_RX_5 82 +#define QUATERNARY_TDM_TX_5 83 +#define QUATERNARY_TDM_RX_6 84 +#define QUATERNARY_TDM_TX_6 85 +#define QUATERNARY_TDM_RX_7 86 +#define QUATERNARY_TDM_TX_7 87 +#define QUINARY_TDM_RX_0 88 +#define QUINARY_TDM_TX_0 89 +#define QUINARY_TDM_RX_1 90 +#define QUINARY_TDM_TX_1 91 +#define QUINARY_TDM_RX_2 92 +#define QUINARY_TDM_TX_2 93 +#define QUINARY_TDM_RX_3 94 +#define QUINARY_TDM_TX_3 95 +#define QUINARY_TDM_RX_4 96 +#define QUINARY_TDM_TX_4 97 +#define QUINARY_TDM_RX_5 98 +#define QUINARY_TDM_TX_5 99 +#define QUINARY_TDM_RX_6 100 +#define QUINARY_TDM_TX_6 101 +#define QUINARY_TDM_RX_7 102 +#define QUINARY_TDM_TX_7 103 +#define DISPLAY_PORT_RX 104 +#define WSA_CODEC_DMA_RX_0 105 +#define WSA_CODEC_DMA_TX_0 106 +#define WSA_CODEC_DMA_RX_1 107 +#define WSA_CODEC_DMA_TX_1 108 +#define WSA_CODEC_DMA_TX_2 109 +#define VA_CODEC_DMA_TX_0 110 +#define VA_CODEC_DMA_TX_1 111 +#define VA_CODEC_DMA_TX_2 112 +#define RX_CODEC_DMA_RX_0 113 +#define TX_CODEC_DMA_TX_0 114 +#define RX_CODEC_DMA_RX_1 115 +#define TX_CODEC_DMA_TX_1 116 +#define RX_CODEC_DMA_RX_2 117 +#define TX_CODEC_DMA_TX_2 118 +#define RX_CODEC_DMA_RX_3 119 +#define TX_CODEC_DMA_TX_3 120 +#define RX_CODEC_DMA_RX_4 121 +#define TX_CODEC_DMA_TX_4 122 +#define RX_CODEC_DMA_RX_5 123 +#define TX_CODEC_DMA_TX_5 124 +#define RX_CODEC_DMA_RX_6 125 +#define RX_CODEC_DMA_RX_7 126 +#define QUINARY_MI2S_RX 127 +#define QUINARY_MI2S_TX 128 + +#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 +#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 +#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 +#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 +#define LPASS_CLK_ID_TER_MI2S_IBIT 5 +#define LPASS_CLK_ID_TER_MI2S_EBIT 6 +#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 +#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 +#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 +#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 +#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 +#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 +#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 +#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 +#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 +#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 +#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 +#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 +#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 +#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 +#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 +#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 +#define LPASS_CLK_ID_QUI_MI2S_OSR 23 +#define LPASS_CLK_ID_PRI_PCM_IBIT 24 +#define LPASS_CLK_ID_PRI_PCM_EBIT 25 +#define LPASS_CLK_ID_SEC_PCM_IBIT 26 +#define LPASS_CLK_ID_SEC_PCM_EBIT 27 +#define LPASS_CLK_ID_TER_PCM_IBIT 28 +#define LPASS_CLK_ID_TER_PCM_EBIT 29 +#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 +#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 +#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 +#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 +#define LPASS_CLK_ID_QUI_PCM_OSR 34 +#define LPASS_CLK_ID_PRI_TDM_IBIT 35 +#define LPASS_CLK_ID_PRI_TDM_EBIT 36 +#define LPASS_CLK_ID_SEC_TDM_IBIT 37 +#define LPASS_CLK_ID_SEC_TDM_EBIT 38 +#define LPASS_CLK_ID_TER_TDM_IBIT 39 +#define LPASS_CLK_ID_TER_TDM_EBIT 40 +#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 +#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 +#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 +#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 +#define LPASS_CLK_ID_QUIN_TDM_OSR 45 +#define LPASS_CLK_ID_MCLK_1 46 +#define LPASS_CLK_ID_MCLK_2 47 +#define LPASS_CLK_ID_MCLK_3 48 +#define LPASS_CLK_ID_MCLK_4 49 +#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 +#define LPASS_CLK_ID_INT_MCLK_0 51 +#define LPASS_CLK_ID_INT_MCLK_1 52 +#define LPASS_CLK_ID_MCLK_5 53 +#define LPASS_CLK_ID_WSA_CORE_MCLK 54 +#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 +#define LPASS_CLK_ID_VA_CORE_MCLK 56 +#define LPASS_CLK_ID_TX_CORE_MCLK 57 +#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 +#define LPASS_CLK_ID_RX_CORE_MCLK 59 +#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 +#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 + +#define LPASS_HW_AVTIMER_VOTE 101 +#define LPASS_HW_MACRO_VOTE 102 +#define LPASS_HW_DCODEC_VOTE 103 + +#define Q6AFE_MAX_CLK_ID 104 + +#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 +#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 + +#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */ diff --git a/include/linux/firmware/cirrus/cs_dsp.h b/include/linux/firmware/cirrus/cs_dsp.h new file mode 100644 index 000000000000..9ad9eaaaa552 --- /dev/null +++ b/include/linux/firmware/cirrus/cs_dsp.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * cs_dsp.h -- Cirrus Logic DSP firmware support + * + * Based on sound/soc/codecs/wm_adsp.h + * + * Copyright 2012 Wolfson Microelectronics plc + * Copyright (C) 2015-2021 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ +#ifndef __CS_DSP_H +#define __CS_DSP_H + +#define CS_ADSP2_REGION_0 BIT(0) +#define CS_ADSP2_REGION_1 BIT(1) +#define CS_ADSP2_REGION_2 BIT(2) +#define CS_ADSP2_REGION_3 BIT(3) +#define CS_ADSP2_REGION_4 BIT(4) +#define CS_ADSP2_REGION_5 BIT(5) +#define CS_ADSP2_REGION_6 BIT(6) +#define CS_ADSP2_REGION_7 BIT(7) +#define CS_ADSP2_REGION_8 BIT(8) +#define CS_ADSP2_REGION_9 BIT(9) +#define CS_ADSP2_REGION_1_9 (CS_ADSP2_REGION_1 | \ + CS_ADSP2_REGION_2 | CS_ADSP2_REGION_3 | \ + CS_ADSP2_REGION_4 | CS_ADSP2_REGION_5 | \ + CS_ADSP2_REGION_6 | CS_ADSP2_REGION_7 | \ + CS_ADSP2_REGION_8 | CS_ADSP2_REGION_9) +#define CS_ADSP2_REGION_ALL (CS_ADSP2_REGION_0 | CS_ADSP2_REGION_1_9) + +#define CS_DSP_DATA_WORD_SIZE 3 + +#define CS_DSP_ACKED_CTL_TIMEOUT_MS 100 +#define CS_DSP_ACKED_CTL_N_QUICKPOLLS 10 +#define CS_DSP_ACKED_CTL_MIN_VALUE 0 +#define CS_DSP_ACKED_CTL_MAX_VALUE 0xFFFFFF + +/** + * struct cs_dsp_region - Describes a logical memory region in DSP address space + * @type: Memory region type + * @base: Address of region + */ +struct cs_dsp_region { + int type; + unsigned int base; +}; + +/** + * struct cs_dsp_alg_region - Describes a logical algorithm region in DSP address space + * @list: List node for internal use + * @alg: Algorithm id + * @type: Memory region type + * @base: Address of region + */ +struct cs_dsp_alg_region { + struct list_head list; + unsigned int alg; + int type; + unsigned int base; +}; + +/** + * struct cs_dsp_coeff_ctl - Describes a coefficient control + * @fw_name: Name of the firmware + * @subname: Name of the control parsed from the WMFW + * @subname_len: Length of subname + * @alg_region: Logical region associated with this control + * @dsp: DSP instance associated with this control + * @enabled: Flag indicating whether control is enabled + * @list: List node for internal use + * @cache: Cached value of the control + * @offset: Offset of control within alg_region + * @len: Length of the cached value + * @set: Flag indicating the value has been written by the user + * @flags: Bitfield of WMFW_CTL_FLAG_ control flags defined in wmfw.h + * @type: One of the WMFW_CTL_TYPE_ control types defined in wmfw.h + * @priv: For use by the client + */ +struct cs_dsp_coeff_ctl { + const char *fw_name; + /* Subname is needed to match with firmware */ + const char *subname; + unsigned int subname_len; + struct cs_dsp_alg_region alg_region; + struct cs_dsp *dsp; + unsigned int enabled:1; + struct list_head list; + void *cache; + unsigned int offset; + size_t len; + unsigned int set:1; + unsigned int flags; + unsigned int type; + + void *priv; +}; + +struct cs_dsp_ops; +struct cs_dsp_client_ops; + +/** + * struct cs_dsp - Configuration and state of a Cirrus Logic DSP + * @name: The name of the DSP instance + * @rev: Revision of the DSP + * @num: DSP instance number + * @type: Type of DSP + * @dev: Driver model representation of the device + * @regmap: Register map of the device + * @ops: Function pointers for internal callbacks + * @client_ops: Function pointers for client callbacks + * @base: Address of the DSP registers + * @base_sysinfo: Address of the sysinfo register (Halo only) + * @sysclk_reg: Address of the sysclk register (ADSP1 only) + * @sysclk_mask: Mask of frequency bits within sysclk register (ADSP1 only) + * @sysclk_shift: Shift of frequency bits within sysclk register (ADSP1 only) + * @alg_regions: List of currently loaded algorithm regions + * @fw_file_name: Filename of the current firmware + * @fw_name: Name of the current firmware + * @fw_id: ID of the current firmware, obtained from the wmfw + * @fw_id_version: Version of the firmware, obtained from the wmfw + * @fw_vendor_id: Vendor of the firmware, obtained from the wmfw + * @mem: DSP memory region descriptions + * @num_mems: Number of memory regions in this DSP + * @fw_ver: Version of the wmfw file format + * @booted: Flag indicating DSP has been configured + * @running: Flag indicating DSP is executing firmware + * @ctl_list: Controls defined within the loaded DSP firmware + * @lock_regions: Enable MPU traps on specified memory regions + * @pwr_lock: Lock used to serialize accesses + * @debugfs_root: Debugfs directory for this DSP instance + * @wmfw_file_name: Filename of the currently loaded firmware + * @bin_file_name: Filename of the currently loaded coefficients + */ +struct cs_dsp { + const char *name; + int rev; + int num; + int type; + struct device *dev; + struct regmap *regmap; + + const struct cs_dsp_ops *ops; + const struct cs_dsp_client_ops *client_ops; + + unsigned int base; + unsigned int base_sysinfo; + unsigned int sysclk_reg; + unsigned int sysclk_mask; + unsigned int sysclk_shift; + + struct list_head alg_regions; + + const char *fw_name; + unsigned int fw_id; + unsigned int fw_id_version; + unsigned int fw_vendor_id; + + const struct cs_dsp_region *mem; + int num_mems; + + int fw_ver; + + bool booted; + bool running; + + struct list_head ctl_list; + + struct mutex pwr_lock; + + unsigned int lock_regions; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_root; + char *wmfw_file_name; + char *bin_file_name; +#endif +}; + +/** + * struct cs_dsp_client_ops - client callbacks + * @control_add: Called under the pwr_lock when a control is created + * @control_remove: Called under the pwr_lock when a control is destroyed + * @post_run: Called under the pwr_lock by cs_dsp_run() + * @post_stop: Called under the pwr_lock by cs_dsp_stop() + * @watchdog_expired: Called when a watchdog expiry is detected + * + * These callbacks give the cs_dsp client an opportunity to respond to events + * or to perform actions atomically. + */ +struct cs_dsp_client_ops { + int (*control_add)(struct cs_dsp_coeff_ctl *ctl); + void (*control_remove)(struct cs_dsp_coeff_ctl *ctl); + int (*post_run)(struct cs_dsp *dsp); + void (*post_stop)(struct cs_dsp *dsp); + void (*watchdog_expired)(struct cs_dsp *dsp); +}; + +int cs_dsp_adsp1_init(struct cs_dsp *dsp); +int cs_dsp_adsp2_init(struct cs_dsp *dsp); +int cs_dsp_halo_init(struct cs_dsp *dsp); + +int cs_dsp_adsp1_power_up(struct cs_dsp *dsp, + const struct firmware *wmfw_firmware, char *wmfw_filename, + const struct firmware *coeff_firmware, char *coeff_filename, + const char *fw_name); +void cs_dsp_adsp1_power_down(struct cs_dsp *dsp); +int cs_dsp_power_up(struct cs_dsp *dsp, + const struct firmware *wmfw_firmware, char *wmfw_filename, + const struct firmware *coeff_firmware, char *coeff_filename, + const char *fw_name); +void cs_dsp_power_down(struct cs_dsp *dsp); +int cs_dsp_run(struct cs_dsp *dsp); +void cs_dsp_stop(struct cs_dsp *dsp); + +void cs_dsp_remove(struct cs_dsp *dsp); + +int cs_dsp_set_dspclk(struct cs_dsp *dsp, unsigned int freq); +void cs_dsp_adsp2_bus_error(struct cs_dsp *dsp); +void cs_dsp_halo_bus_error(struct cs_dsp *dsp); +void cs_dsp_halo_wdt_expire(struct cs_dsp *dsp); + +void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root); +void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp); + +int cs_dsp_coeff_write_acked_control(struct cs_dsp_coeff_ctl *ctl, unsigned int event_id); +int cs_dsp_coeff_write_ctrl(struct cs_dsp_coeff_ctl *ctl, const void *buf, size_t len); +int cs_dsp_coeff_read_ctrl(struct cs_dsp_coeff_ctl *ctl, void *buf, size_t len); +struct cs_dsp_coeff_ctl *cs_dsp_get_ctl(struct cs_dsp *dsp, const char *name, int type, + unsigned int alg); + +int cs_dsp_read_raw_data_block(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, + unsigned int num_words, __be32 *data); +int cs_dsp_read_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 *data); +int cs_dsp_write_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 data); +void cs_dsp_remove_padding(u32 *buf, int nwords); + +struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp, + int type, unsigned int id); + +const char *cs_dsp_mem_region_name(unsigned int type); + +#endif diff --git a/include/linux/firmware/cirrus/wmfw.h b/include/linux/firmware/cirrus/wmfw.h new file mode 100644 index 000000000000..a19bf7c6fc8b --- /dev/null +++ b/include/linux/firmware/cirrus/wmfw.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * wmfw.h - Wolfson firmware format information + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> + */ + +#ifndef __WMFW_H +#define __WMFW_H + +#include <linux/types.h> + +#define WMFW_MAX_ALG_NAME 256 +#define WMFW_MAX_ALG_DESCR_NAME 256 + +#define WMFW_MAX_COEFF_NAME 256 +#define WMFW_MAX_COEFF_DESCR_NAME 256 + +#define WMFW_CTL_FLAG_SYS 0x8000 +#define WMFW_CTL_FLAG_VOLATILE 0x0004 +#define WMFW_CTL_FLAG_WRITEABLE 0x0002 +#define WMFW_CTL_FLAG_READABLE 0x0001 + +#define WMFW_CTL_TYPE_BYTES 0x0004 /* byte control */ + +/* Non-ALSA coefficient types start at 0x1000 */ +#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */ +#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */ +#define WMFW_CTL_TYPE_HOST_BUFFER 0x1002 /* host buffer pointer */ + +struct wmfw_header { + char magic[4]; + __le32 len; + __le16 rev; + u8 core; + u8 ver; +} __packed; + +struct wmfw_footer { + __le64 timestamp; + __le32 checksum; +} __packed; + +struct wmfw_adsp1_sizes { + __le32 dm; + __le32 pm; + __le32 zm; +} __packed; + +struct wmfw_adsp2_sizes { + __le32 xm; + __le32 ym; + __le32 pm; + __le32 zm; +} __packed; + +struct wmfw_region { + union { + __be32 type; + __le32 offset; + }; + __le32 len; + u8 data[]; +} __packed; + +struct wmfw_id_hdr { + __be32 core_id; + __be32 core_rev; + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_v3_id_hdr { + __be32 core_id; + __be32 block_rev; + __be32 vendor_id; + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_adsp1_id_hdr { + struct wmfw_id_hdr fw; + __be32 zm; + __be32 dm; + __be32 n_algs; +} __packed; + +struct wmfw_adsp2_id_hdr { + struct wmfw_id_hdr fw; + __be32 zm; + __be32 xm; + __be32 ym; + __be32 n_algs; +} __packed; + +struct wmfw_halo_id_hdr { + struct wmfw_v3_id_hdr fw; + __be32 xm_base; + __be32 xm_size; + __be32 ym_base; + __be32 ym_size; + __be32 n_algs; +} __packed; + +struct wmfw_alg_hdr { + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_adsp1_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 zm; + __be32 dm; +} __packed; + +struct wmfw_adsp2_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 zm; + __be32 xm; + __be32 ym; +} __packed; + +struct wmfw_halo_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 xm_base; + __be32 xm_size; + __be32 ym_base; + __be32 ym_size; +} __packed; + +struct wmfw_adsp_alg_data { + __le32 id; + u8 name[WMFW_MAX_ALG_NAME]; + u8 descr[WMFW_MAX_ALG_DESCR_NAME]; + __le32 ncoeff; + u8 data[]; +} __packed; + +struct wmfw_adsp_coeff_data { + struct { + __le16 offset; + __le16 type; + __le32 size; + } hdr; + u8 name[WMFW_MAX_COEFF_NAME]; + u8 descr[WMFW_MAX_COEFF_DESCR_NAME]; + __le16 ctl_type; + __le16 flags; + __le32 len; + u8 data[]; +} __packed; + +struct wmfw_coeff_hdr { + u8 magic[4]; + __le32 len; + union { + __be32 rev; + __le32 ver; + }; + union { + __be32 core; + __le32 core_ver; + }; + u8 data[]; +} __packed; + +struct wmfw_coeff_item { + __le16 offset; + __le16 type; + __le32 id; + __le32 ver; + __le32 sr; + __le32 len; + u8 data[]; +} __packed; + +#define WMFW_ADSP1 1 +#define WMFW_ADSP2 2 +#define WMFW_HALO 4 + +#define WMFW_ABSOLUTE 0xf0 +#define WMFW_ALGORITHM_DATA 0xf2 +#define WMFW_METADATA 0xfc +#define WMFW_NAME_TEXT 0xfe +#define WMFW_INFO_TEXT 0xff + +#define WMFW_ADSP1_PM 2 +#define WMFW_ADSP1_DM 3 +#define WMFW_ADSP1_ZM 4 + +#define WMFW_ADSP2_PM 2 +#define WMFW_ADSP2_ZM 4 +#define WMFW_ADSP2_XM 5 +#define WMFW_ADSP2_YM 6 + +#define WMFW_HALO_PM_PACKED 0x10 +#define WMFW_HALO_XM_PACKED 0x11 +#define WMFW_HALO_YM_PACKED 0x12 + +#endif diff --git a/include/linux/soc/qcom/apr.h b/include/linux/soc/qcom/apr.h index 137f9f2ac4c3..23c5b30f3511 100644 --- a/include/linux/soc/qcom/apr.h +++ b/include/linux/soc/qcom/apr.h @@ -7,6 +7,7 @@ #include <linux/device.h> #include <linux/mod_devicetable.h> #include <dt-bindings/soc/qcom,apr.h> +#include <dt-bindings/soc/qcom,gpr.h> extern struct bus_type aprbus; @@ -75,10 +76,65 @@ struct apr_resp_pkt { int payload_size; }; +struct gpr_hdr { + uint32_t version:4; + uint32_t hdr_size:4; + uint32_t pkt_size:24; + uint32_t dest_domain:8; + uint32_t src_domain:8; + uint32_t reserved:16; + uint32_t src_port; + uint32_t dest_port; + uint32_t token; + uint32_t opcode; +} __packed; + +struct gpr_pkt { + struct gpr_hdr hdr; + uint32_t payload[]; +}; + +struct gpr_resp_pkt { + struct gpr_hdr hdr; + void *payload; + int payload_size; +}; + +#define GPR_HDR_SIZE sizeof(struct gpr_hdr) +#define GPR_PKT_VER 0x0 +#define GPR_PKT_HEADER_WORD_SIZE ((sizeof(struct gpr_pkt) + 3) >> 2) +#define GPR_PKT_HEADER_BYTE_SIZE (GPR_PKT_HEADER_WORD_SIZE << 2) + +#define GPR_BASIC_RSP_RESULT 0x02001005 + +struct gpr_ibasic_rsp_result_t { + uint32_t opcode; + uint32_t status; +}; + +#define GPR_BASIC_EVT_ACCEPTED 0x02001006 + +struct gpr_ibasic_rsp_accepted_t { + uint32_t opcode; +}; + /* Bits 0 to 15 -- Minor version, Bits 16 to 31 -- Major version */ #define APR_SVC_MAJOR_VERSION(v) ((v >> 16) & 0xFF) #define APR_SVC_MINOR_VERSION(v) (v & 0xFF) +typedef int (*gpr_port_cb) (struct gpr_resp_pkt *d, void *priv, int op); +struct packet_router; +struct pkt_router_svc { + struct device *dev; + gpr_port_cb callback; + struct packet_router *pr; + spinlock_t lock; + int id; + void *priv; +}; + +typedef struct pkt_router_svc gpr_port_t; + struct apr_device { struct device dev; uint16_t svc_id; @@ -86,21 +142,26 @@ struct apr_device { uint32_t version; char name[APR_NAME_SIZE]; const char *service_path; - spinlock_t lock; + struct pkt_router_svc svc; struct list_head node; }; +typedef struct apr_device gpr_device_t; + #define to_apr_device(d) container_of(d, struct apr_device, dev) +#define svc_to_apr_device(d) container_of(d, struct apr_device, svc) struct apr_driver { int (*probe)(struct apr_device *sl); int (*remove)(struct apr_device *sl); int (*callback)(struct apr_device *a, struct apr_resp_pkt *d); + int (*gpr_callback)(struct gpr_resp_pkt *d, void *data, int op); struct device_driver driver; const struct apr_device_id *id_table; }; +typedef struct apr_driver gpr_driver_t; #define to_apr_driver(d) container_of(d, struct apr_driver, driver) /* @@ -123,7 +184,14 @@ void apr_driver_unregister(struct apr_driver *drv); #define module_apr_driver(__apr_driver) \ module_driver(__apr_driver, apr_driver_register, \ apr_driver_unregister) +#define module_gpr_driver(__gpr_driver) module_apr_driver(__gpr_driver) int apr_send_pkt(struct apr_device *adev, struct apr_pkt *pkt); +gpr_port_t *gpr_alloc_port(gpr_device_t *gdev, struct device *dev, + gpr_port_cb cb, void *priv); +void gpr_free_port(gpr_port_t *port); +int gpr_send_port_pkt(gpr_port_t *port, struct gpr_pkt *pkt); +int gpr_send_pkt(gpr_device_t *gdev, struct gpr_pkt *pkt); + #endif /* __QCOM_APR_H_ */ diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h new file mode 100644 index 000000000000..1f1e3c6c9be1 --- /dev/null +++ b/include/sound/cs35l41.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/cs35l41.h -- Platform data for CS35L41 + * + * Copyright (c) 2017-2021 Cirrus Logic Inc. + * + * Author: David Rhodes <david.rhodes@cirrus.com> + */ + +#ifndef __CS35L41_H +#define __CS35L41_H + +enum cs35l41_clk_ids { + CS35L41_CLKID_SCLK = 0, + CS35L41_CLKID_LRCLK = 1, + CS35L41_CLKID_MCLK = 4, +}; + +struct cs35l41_irq_cfg { + bool irq_pol_inv; + bool irq_out_en; + int irq_src_sel; +}; + +struct cs35l41_platform_data { + int bst_ind; + int bst_ipk; + int bst_cap; + int dout_hiz; + struct cs35l41_irq_cfg irq_config1; + struct cs35l41_irq_cfg irq_config2; +}; + +#endif /* __CS35L41_H */ diff --git a/include/sound/graph_card.h b/include/sound/graph_card.h index 6f10bfb0d5ee..4c8b94c77b8e 100644 --- a/include/sound/graph_card.h +++ b/include/sound/graph_card.h @@ -9,6 +9,27 @@ #include <sound/simple_card_utils.h> +typedef int (*GRAPH2_CUSTOM)(struct asoc_simple_priv *priv, + struct device_node *lnk, + struct link_info *li); + +struct graph2_custom_hooks { + int (*hook_pre)(struct asoc_simple_priv *priv); + int (*hook_post)(struct asoc_simple_priv *priv); + GRAPH2_CUSTOM custom_normal; + GRAPH2_CUSTOM custom_dpcm; + GRAPH2_CUSTOM custom_c2c; +}; + int audio_graph_parse_of(struct asoc_simple_priv *priv, struct device *dev); +int audio_graph2_parse_of(struct asoc_simple_priv *priv, struct device *dev, + struct graph2_custom_hooks *hooks); + +int audio_graph2_link_normal(struct asoc_simple_priv *priv, + struct device_node *lnk, struct link_info *li); +int audio_graph2_link_dpcm(struct asoc_simple_priv *priv, + struct device_node *lnk, struct link_info *li); +int audio_graph2_link_c2c(struct asoc_simple_priv *priv, + struct device_node *lnk, struct link_info *li); #endif /* __GRAPH_CARD_H */ diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h index 375581634143..d4e31ea16aba 100644 --- a/include/sound/hdaudio_ext.h +++ b/include/sound/hdaudio_ext.h @@ -88,6 +88,8 @@ struct hdac_ext_stream *snd_hdac_ext_stream_assign(struct hdac_bus *bus, struct snd_pcm_substream *substream, int type); void snd_hdac_ext_stream_release(struct hdac_ext_stream *azx_dev, int type); +void snd_hdac_ext_stream_decouple_locked(struct hdac_bus *bus, + struct hdac_ext_stream *azx_dev, bool decouple); void snd_hdac_ext_stream_decouple(struct hdac_bus *bus, struct hdac_ext_stream *azx_dev, bool decouple); void snd_hdac_ext_stop_streams(struct hdac_bus *bus); diff --git a/include/sound/memalloc.h b/include/sound/memalloc.h index b197e3f431c1..653dfffb3ac8 100644 --- a/include/sound/memalloc.h +++ b/include/sound/memalloc.h @@ -9,16 +9,20 @@ #ifndef __SOUND_MEMALLOC_H #define __SOUND_MEMALLOC_H +#include <linux/dma-direction.h> #include <asm/page.h> struct device; struct vm_area_struct; +struct sg_table; /* * buffer device info */ struct snd_dma_device { int type; /* SNDRV_DMA_TYPE_XXX */ + enum dma_data_direction dir; /* DMA direction */ + bool need_sync; /* explicit sync needed? */ struct device *dev; /* generic device */ }; @@ -32,19 +36,21 @@ struct snd_dma_device { #define SNDRV_DMA_TYPE_CONTINUOUS 1 /* continuous no-DMA memory */ #define SNDRV_DMA_TYPE_DEV 2 /* generic device continuous */ #define SNDRV_DMA_TYPE_DEV_WC 5 /* continuous write-combined */ -#ifdef CONFIG_SND_DMA_SGBUF -#define SNDRV_DMA_TYPE_DEV_SG 3 /* generic device SG-buffer */ -#define SNDRV_DMA_TYPE_DEV_WC_SG 6 /* SG write-combined */ -#else -#define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_DEV /* no SG-buf support */ -#define SNDRV_DMA_TYPE_DEV_WC_SG SNDRV_DMA_TYPE_DEV_WC -#endif #ifdef CONFIG_GENERIC_ALLOCATOR #define SNDRV_DMA_TYPE_DEV_IRAM 4 /* generic device iram-buffer */ #else #define SNDRV_DMA_TYPE_DEV_IRAM SNDRV_DMA_TYPE_DEV #endif #define SNDRV_DMA_TYPE_VMALLOC 7 /* vmalloc'ed buffer */ +#define SNDRV_DMA_TYPE_NONCONTIG 8 /* non-coherent SG buffer */ +#define SNDRV_DMA_TYPE_NONCOHERENT 9 /* non-coherent buffer */ +#ifdef CONFIG_SND_DMA_SGBUF +#define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_NONCONTIG +#define SNDRV_DMA_TYPE_DEV_WC_SG 6 /* SG write-combined */ +#else +#define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_DEV /* no SG-buf support */ +#define SNDRV_DMA_TYPE_DEV_WC_SG SNDRV_DMA_TYPE_DEV_WC +#endif /* * info for buffer allocation @@ -66,22 +72,52 @@ static inline unsigned int snd_sgbuf_aligned_pages(size_t size) } /* allocate/release a buffer */ -int snd_dma_alloc_pages(int type, struct device *dev, size_t size, - struct snd_dma_buffer *dmab); +int snd_dma_alloc_dir_pages(int type, struct device *dev, + enum dma_data_direction dir, size_t size, + struct snd_dma_buffer *dmab); + +static inline int snd_dma_alloc_pages(int type, struct device *dev, + size_t size, struct snd_dma_buffer *dmab) +{ + return snd_dma_alloc_dir_pages(type, dev, DMA_BIDIRECTIONAL, size, dmab); +} + int snd_dma_alloc_pages_fallback(int type, struct device *dev, size_t size, struct snd_dma_buffer *dmab); void snd_dma_free_pages(struct snd_dma_buffer *dmab); int snd_dma_buffer_mmap(struct snd_dma_buffer *dmab, struct vm_area_struct *area); +enum snd_dma_sync_mode { SNDRV_DMA_SYNC_CPU, SNDRV_DMA_SYNC_DEVICE }; +#ifdef CONFIG_HAS_DMA +void snd_dma_buffer_sync(struct snd_dma_buffer *dmab, + enum snd_dma_sync_mode mode); +#else +static inline void snd_dma_buffer_sync(struct snd_dma_buffer *dmab, + enum snd_dma_sync_mode mode) {} +#endif + dma_addr_t snd_sgbuf_get_addr(struct snd_dma_buffer *dmab, size_t offset); struct page *snd_sgbuf_get_page(struct snd_dma_buffer *dmab, size_t offset); unsigned int snd_sgbuf_get_chunk_size(struct snd_dma_buffer *dmab, unsigned int ofs, unsigned int size); /* device-managed memory allocator */ -struct snd_dma_buffer *snd_devm_alloc_pages(struct device *dev, int type, - size_t size); +struct snd_dma_buffer *snd_devm_alloc_dir_pages(struct device *dev, int type, + enum dma_data_direction dir, + size_t size); + +static inline struct snd_dma_buffer * +snd_devm_alloc_pages(struct device *dev, int type, size_t size) +{ + return snd_devm_alloc_dir_pages(dev, type, DMA_BIDIRECTIONAL, size); +} + +static inline struct sg_table * +snd_dma_noncontig_sg_table(struct snd_dma_buffer *dmab) +{ + return dmab->private_data; +} #endif /* __SOUND_MEMALLOC_H */ diff --git a/include/sound/rt5682s.h b/include/sound/rt5682s.h new file mode 100644 index 000000000000..accfbc2dcdd2 --- /dev/null +++ b/include/sound/rt5682s.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5682s.h -- Platform data for RT5682I-VS + * + * Copyright 2021 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5682S_H +#define __LINUX_SND_RT5682S_H + +enum rt5682s_dmic1_data_pin { + RT5682S_DMIC1_DATA_NULL, + RT5682S_DMIC1_DATA_GPIO2, + RT5682S_DMIC1_DATA_GPIO5, +}; + +enum rt5682s_dmic1_clk_pin { + RT5682S_DMIC1_CLK_NULL, + RT5682S_DMIC1_CLK_GPIO1, + RT5682S_DMIC1_CLK_GPIO3, +}; + +enum rt5682s_jd_src { + RT5682S_JD_NULL, + RT5682S_JD1, +}; + +enum rt5682s_dai_clks { + RT5682S_DAI_WCLK_IDX, + RT5682S_DAI_BCLK_IDX, + RT5682S_DAI_NUM_CLKS, +}; + +struct rt5682s_platform_data { + + int ldo1_en; /* GPIO for LDO1_EN */ + + enum rt5682s_dmic1_data_pin dmic1_data_pin; + enum rt5682s_dmic1_clk_pin dmic1_clk_pin; + enum rt5682s_jd_src jd_src; + unsigned int dmic_clk_rate; + unsigned int dmic_delay; + bool dmic_clk_driving_high; + + const char *dai_clk_names[RT5682S_DAI_NUM_CLKS]; +}; + +#endif diff --git a/include/sound/simple_card_utils.h b/include/sound/simple_card_utils.h index 51b3b485a92e..df430f1c2a10 100644 --- a/include/sound/simple_card_utils.h +++ b/include/sound/simple_card_utils.h @@ -42,6 +42,7 @@ struct prop_nums { int cpus; int codecs; int platforms; + int c2c; }; struct asoc_simple_priv { @@ -54,6 +55,7 @@ struct asoc_simple_priv { struct snd_soc_dai_link_component *platforms; struct asoc_simple_data adata; struct snd_soc_codec_conf *codec_conf; + struct snd_soc_pcm_stream *c2c_conf; struct prop_nums num; unsigned int mclk_fs; } *dai_props; @@ -64,6 +66,7 @@ struct asoc_simple_priv { struct snd_soc_dai_link_component *dlcs; struct snd_soc_dai_link_component dummy; struct snd_soc_codec_conf *codec_conf; + struct snd_soc_pcm_stream *c2c_conf; struct gpio_desc *pa_gpio; const struct snd_soc_ops *ops; unsigned int dpcm_selectable:1; @@ -115,7 +118,7 @@ struct asoc_simple_priv { ((codec) = simple_props_to_dai_codec(props, i)); \ (i)++) -#define SNDRV_MAX_LINKS 128 +#define SNDRV_MAX_LINKS 512 struct link_info { int link; /* number of link */ @@ -180,6 +183,7 @@ int asoc_simple_init_priv(struct asoc_simple_priv *priv, int asoc_simple_remove(struct platform_device *pdev); int asoc_graph_card_probe(struct snd_soc_card *card); +int asoc_graph_is_ports0(struct device_node *port); #ifdef DEBUG static inline void asoc_simple_debug_dai(struct asoc_simple_priv *priv, diff --git a/include/sound/soc-acpi.h b/include/sound/soc-acpi.h index 2f3fa385c092..31f4c4f9aeea 100644 --- a/include/sound/soc-acpi.h +++ b/include/sound/soc-acpi.h @@ -129,6 +129,8 @@ struct snd_soc_acpi_link_adr { * all firmware/topology related fields. * * @id: ACPI ID (usually the codec's) used to find a matching machine driver. + * @comp_ids: list of compatible audio codecs using the same machine driver, + * firmware and topology * @link_mask: describes required board layout, e.g. for SoundWire. * @links: array of link _ADR descriptors, null terminated. * @drv_name: machine driver name @@ -146,6 +148,7 @@ struct snd_soc_acpi_link_adr { /* Descriptor for SST ASoC machine driver */ struct snd_soc_acpi_mach { const u8 id[ACPI_ID_LEN]; + const struct snd_soc_acpi_codecs *comp_ids; const u32 link_mask; const struct snd_soc_acpi_link_adr *links; const char *drv_name; diff --git a/include/sound/soc-component.h b/include/sound/soc-component.h index 8c4d6830597f..a4317144ab62 100644 --- a/include/sound/soc-component.h +++ b/include/sound/soc-component.h @@ -220,17 +220,15 @@ struct snd_soc_component { int (*init)(struct snd_soc_component *component); /* function mark */ - struct snd_pcm_substream *mark_module; + void *mark_module; struct snd_pcm_substream *mark_open; struct snd_pcm_substream *mark_hw_params; struct snd_pcm_substream *mark_trigger; struct snd_compr_stream *mark_compr_open; void *mark_pm; -#ifdef CONFIG_DEBUG_FS struct dentry *debugfs_root; const char *debugfs_prefix; -#endif }; #define for_each_component_dais(component, dai)\ @@ -335,6 +333,11 @@ static inline int snd_soc_component_cache_sync( return regcache_sync(component->regmap); } +static inline int snd_soc_component_is_codec(struct snd_soc_component *component) +{ + return component->driver->non_legacy_dai_naming; +} + void snd_soc_component_set_aux(struct snd_soc_component *component, struct snd_soc_aux_dev *aux); int snd_soc_component_init(struct snd_soc_component *component); @@ -391,15 +394,13 @@ void snd_soc_component_exit_regmap(struct snd_soc_component *component); #define snd_soc_component_module_get_when_open(component, substream) \ snd_soc_component_module_get(component, substream, 1) int snd_soc_component_module_get(struct snd_soc_component *component, - struct snd_pcm_substream *substream, - int upon_open); + void *mark, int upon_open); #define snd_soc_component_module_put_when_remove(component) \ snd_soc_component_module_put(component, NULL, 0, 0) #define snd_soc_component_module_put_when_close(component, substream, rollback) \ snd_soc_component_module_put(component, substream, 1, rollback) void snd_soc_component_module_put(struct snd_soc_component *component, - struct snd_pcm_substream *substream, - int upon_open, int rollback); + void *mark, int upon_open, int rollback); static inline void snd_soc_component_set_drvdata(struct snd_soc_component *c, void *data) @@ -455,8 +456,10 @@ int snd_soc_component_of_xlate_dai_id(struct snd_soc_component *component, int snd_soc_component_of_xlate_dai_name(struct snd_soc_component *component, const struct of_phandle_args *args, const char **dai_name); -int snd_soc_component_compr_open(struct snd_compr_stream *cstream); -void snd_soc_component_compr_free(struct snd_compr_stream *cstream, +int snd_soc_component_compr_open(struct snd_soc_component *component, + struct snd_compr_stream *cstream); +void snd_soc_component_compr_free(struct snd_soc_component *component, + struct snd_compr_stream *cstream, int rollback); int snd_soc_component_compr_trigger(struct snd_compr_stream *cstream, int cmd); int snd_soc_component_compr_set_params(struct snd_compr_stream *cstream, diff --git a/include/sound/soc-dpcm.h b/include/sound/soc-dpcm.h index e296a3949b18..bc7af90099a8 100644 --- a/include/sound/soc-dpcm.h +++ b/include/sound/soc-dpcm.h @@ -159,6 +159,7 @@ int dpcm_be_dai_trigger(struct snd_soc_pcm_runtime *fe, int stream, int cmd); int dpcm_be_dai_prepare(struct snd_soc_pcm_runtime *fe, int stream); int dpcm_dapm_stream_event(struct snd_soc_pcm_runtime *fe, int dir, int event); +bool dpcm_end_walk_at_be(struct snd_soc_dapm_widget *widget, enum snd_soc_dapm_direction dir); #define dpcm_be_dai_startup_rollback(fe, stream, last) \ dpcm_be_dai_stop(fe, stream, 0, last) diff --git a/include/sound/soc-topology.h b/include/sound/soc-topology.h index 4afd667e124c..b4b896f83b94 100644 --- a/include/sound/soc-topology.h +++ b/include/sound/soc-topology.h @@ -151,7 +151,7 @@ struct snd_soc_tplg_ops { struct snd_soc_tplg_hdr *); /* completion - called at completion of firmware loading */ - void (*complete)(struct snd_soc_component *); + int (*complete)(struct snd_soc_component *comp); /* manifest - optional to inform component of manifest */ int (*manifest)(struct snd_soc_component *, int index, @@ -188,8 +188,7 @@ int snd_soc_tplg_widget_bind_event(struct snd_soc_dapm_widget *w, #else -static inline int snd_soc_tplg_component_remove(struct snd_soc_component *comp, - u32 index) +static inline int snd_soc_tplg_component_remove(struct snd_soc_component *comp) { return 0; } diff --git a/include/sound/sof.h b/include/sound/sof.h index 6a1cd8e783d8..23b374311d16 100644 --- a/include/sound/sof.h +++ b/include/sound/sof.h @@ -74,11 +74,6 @@ struct sof_dev_desc { int resindex_pcicfg_base; int resindex_imr_base; int irqindex_host_ipc; - int resindex_dma_base; - - /* DMA only valid when resindex_dma_base != -1*/ - int dma_engine; - int dma_size; /* IPC timeouts in ms */ int ipc_timeout; diff --git a/include/sound/sof/dai-intel.h b/include/sound/sof/dai-intel.h index 136adf6686e2..7a266f41983c 100644 --- a/include/sound/sof/dai-intel.h +++ b/include/sound/sof/dai-intel.h @@ -48,6 +48,10 @@ #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4) /* bclk idle */ #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) +/* mclk early start */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES BIT(6) +/* bclk early start */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES BIT(7) /* DMIC max. four controllers for eight microphone channels */ #define SOF_DAI_INTEL_DMIC_NUM_CTRL 4 diff --git a/include/sound/sof/dai.h b/include/sound/sof/dai.h index 6bb403e8c5ee..9625f47557b8 100644 --- a/include/sound/sof/dai.h +++ b/include/sound/sof/dai.h @@ -50,6 +50,13 @@ #define SOF_DAI_FMT_INV_MASK 0x0f00 #define SOF_DAI_FMT_CLOCK_PROVIDER_MASK 0xf000 +/* DAI_CONFIG flags */ +#define SOF_DAI_CONFIG_FLAGS_MASK 0x3 +#define SOF_DAI_CONFIG_FLAGS_NONE (0 << 0) /**< DAI_CONFIG sent without stage information */ +#define SOF_DAI_CONFIG_FLAGS_HW_PARAMS (1 << 0) /**< DAI_CONFIG sent during hw_params stage */ +#define SOF_DAI_CONFIG_FLAGS_HW_FREE (2 << 0) /**< DAI_CONFIG sent during hw_free stage */ +#define SOF_DAI_CONFIG_FLAGS_RFU (3 << 0) /**< not used, reserved for future use */ + /** \brief Types of DAI */ enum sof_ipc_dai_type { SOF_DAI_INTEL_NONE = 0, /**< None */ @@ -69,7 +76,8 @@ struct sof_ipc_dai_config { /* physical protocol and clocking */ uint16_t format; /**< SOF_DAI_FMT_ */ - uint16_t reserved16; /**< alignment */ + uint8_t group_id; /**< group ID, 0 means no group (ABI 3.17) */ + uint8_t flags; /**< SOF_DAI_CONFIG_FLAGS_ (ABI 3.19) */ /* reserved for future use */ uint32_t reserved[8]; diff --git a/include/uapi/sound/asound.h b/include/uapi/sound/asound.h index 5859ca0a1439..5fbb79e30819 100644 --- a/include/uapi/sound/asound.h +++ b/include/uapi/sound/asound.h @@ -1002,7 +1002,7 @@ typedef int __bitwise snd_ctl_elem_iface_t; #define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1) #define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE) #define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2) /* control value may be changed without a notification */ -// (1 << 3) is unused. +/* (1 << 3) is unused. */ #define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4) /* TLV read is possible */ #define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5) /* TLV write is possible */ #define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE) diff --git a/include/uapi/sound/firewire.h b/include/uapi/sound/firewire.h index ae12826ed641..39cf6eb75940 100644 --- a/include/uapi/sound/firewire.h +++ b/include/uapi/sound/firewire.h @@ -13,6 +13,7 @@ #define SNDRV_FIREWIRE_EVENT_DIGI00X_MESSAGE 0x746e736c #define SNDRV_FIREWIRE_EVENT_MOTU_NOTIFICATION 0x64776479 #define SNDRV_FIREWIRE_EVENT_TASCAM_CONTROL 0x7473636d +#define SNDRV_FIREWIRE_EVENT_MOTU_REGISTER_DSP_CHANGE 0x4d545244 struct snd_firewire_event_common { unsigned int type; /* SNDRV_FIREWIRE_EVENT_xxx */ @@ -65,6 +66,12 @@ struct snd_firewire_event_tascam_control { struct snd_firewire_tascam_change changes[0]; }; +struct snd_firewire_event_motu_register_dsp_change { + unsigned int type; + __u32 count; /* The number of changes. */ + __u32 changes[]; /* Encoded event for change of register DSP. */ +}; + union snd_firewire_event { struct snd_firewire_event_common common; struct snd_firewire_event_lock_status lock_status; @@ -73,6 +80,7 @@ union snd_firewire_event { struct snd_firewire_event_digi00x_message digi00x_message; struct snd_firewire_event_tascam_control tascam_control; struct snd_firewire_event_motu_notification motu_notification; + struct snd_firewire_event_motu_register_dsp_change motu_register_dsp_change; }; @@ -80,6 +88,9 @@ union snd_firewire_event { #define SNDRV_FIREWIRE_IOCTL_LOCK _IO('H', 0xf9) #define SNDRV_FIREWIRE_IOCTL_UNLOCK _IO('H', 0xfa) #define SNDRV_FIREWIRE_IOCTL_TASCAM_STATE _IOR('H', 0xfb, struct snd_firewire_tascam_state) +#define SNDRV_FIREWIRE_IOCTL_MOTU_REGISTER_DSP_METER _IOR('H', 0xfc, struct snd_firewire_motu_register_dsp_meter) +#define SNDRV_FIREWIRE_IOCTL_MOTU_COMMAND_DSP_METER _IOR('H', 0xfd, struct snd_firewire_motu_command_dsp_meter) +#define SNDRV_FIREWIRE_IOCTL_MOTU_REGISTER_DSP_PARAMETER _IOR('H', 0xfe, struct snd_firewire_motu_register_dsp_parameter) #define SNDRV_FIREWIRE_TYPE_DICE 1 #define SNDRV_FIREWIRE_TYPE_FIREWORKS 2 @@ -108,4 +119,143 @@ struct snd_firewire_tascam_state { __be32 data[SNDRV_FIREWIRE_TASCAM_STATE_COUNT]; }; +/* + * In below MOTU models, software is allowed to control their DSP by accessing to registers. + * - 828mk2 + * - 896hd + * - Traveler + * - 8 pre + * - Ultralite + * - 4 pre + * - Audio Express + * + * On the other hand, the status of DSP is split into specific messages included in the sequence of + * isochronous packet. ALSA firewire-motu driver gathers the messages and allow userspace applications + * to read it via ioctl. In 828mk2, 896hd, and Traveler, hardware meter for all of physical inputs + * are put into the message, while one pair of physical outputs is selected. The selection is done by + * LSB one byte in asynchronous write quadlet transaction to 0x'ffff'f000'0b2c. + * + * I note that V3HD/V4HD uses asynchronous transaction for the purpose. The destination address is + * registered to 0x'ffff'f000'0b38 and '0b3c by asynchronous write quadlet request. The size of + * message differs between 23 and 51 quadlets. For the case, the number of mixer bus can be extended + * up to 12. + */ + +#define SNDRV_FIREWIRE_MOTU_REGISTER_DSP_METER_INPUT_COUNT 24 +#define SNDRV_FIREWIRE_MOTU_REGISTER_DSP_METER_OUTPUT_COUNT 24 +#define SNDRV_FIREWIRE_MOTU_REGISTER_DSP_METER_COUNT \ + (SNDRV_FIREWIRE_MOTU_REGISTER_DSP_METER_INPUT_COUNT + SNDRV_FIREWIRE_MOTU_REGISTER_DSP_METER_OUTPUT_COUNT) + +/** + * struct snd_firewire_motu_register_dsp_meter - the container for meter information in DSP + * controlled by register access + * @data: Signal level meters. The mapping between position and input/output channel is + * model-dependent. + * + * The structure expresses the part of DSP status for hardware meter. The u8 storage includes linear + * value for audio signal level between 0x00 and 0x7f. + */ +struct snd_firewire_motu_register_dsp_meter { + __u8 data[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_METER_COUNT]; +}; + +#define SNDRV_FIREWIRE_MOTU_REGISTER_DSP_MIXER_COUNT 4 +#define SNDRV_FIREWIRE_MOTU_REGISTER_DSP_MIXER_SRC_COUNT 20 +#define SNDRV_FIREWIRE_MOTU_REGISTER_DSP_INPUT_COUNT 10 +#define SNDRV_FIREWIRE_MOTU_REGISTER_DSP_ALIGNED_INPUT_COUNT (SNDRV_FIREWIRE_MOTU_REGISTER_DSP_INPUT_COUNT + 2) + +/** + * snd_firewire_motu_register_dsp_parameter - the container for parameters of DSP controlled + * by register access. + * @mixer.source.gain: The gain of source to mixer. + * @mixer.source.pan: The L/R balance of source to mixer. + * @mixer.source.flag: The flag of source to mixer, including mute, solo. + * @mixer.source.paired_balance: The L/R balance of paired source to mixer, only for 4 pre and + * Audio Express. + * @mixer.source.paired_width: The width of paired source to mixer, only for 4 pre and + * Audio Express. + * @mixer.output.paired_volume: The volume of paired output from mixer. + * @mixer.output.paired_flag: The flag of paired output from mixer. + * @output.main_paired_volume: The volume of paired main output. + * @output.hp_paired_volume: The volume of paired hp output. + * @output.hp_paired_assignment: The source assigned to paired hp output. + * @output.reserved: Padding for 32 bit alignment for future extension. + * @line_input.boost_flag: The flags of boost for line inputs, only for 828mk2 and Traveler. + * @line_input.nominal_level_flag: The flags of nominal level for line inputs, only for 828mk2 and + * Traveler. + * @line_input.reserved: Padding for 32 bit alignment for future extension. + * @input.gain_and_invert: The value including gain and invert for input, only for Ultralite, 4 pre + * and Audio Express. + * @input.flag: The flag of input; e.g. jack detection, phantom power, and pad, only for Ultralite, + * 4 pre and Audio express. + * @reserved: Padding so that the size of structure is kept to 512 byte, but for future extension. + * + * The structure expresses the set of parameters for DSP controlled by register access. + */ +struct snd_firewire_motu_register_dsp_parameter { + struct { + struct { + __u8 gain[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_MIXER_SRC_COUNT]; + __u8 pan[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_MIXER_SRC_COUNT]; + __u8 flag[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_MIXER_SRC_COUNT]; + __u8 paired_balance[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_MIXER_SRC_COUNT]; + __u8 paired_width[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_MIXER_SRC_COUNT]; + } source[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_MIXER_COUNT]; + struct { + __u8 paired_volume[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_MIXER_COUNT]; + __u8 paired_flag[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_MIXER_COUNT]; + } output; + } mixer; + struct { + __u8 main_paired_volume; + __u8 hp_paired_volume; + __u8 hp_paired_assignment; + __u8 reserved[5]; + } output; + struct { + __u8 boost_flag; + __u8 nominal_level_flag; + __u8 reserved[6]; + } line_input; + struct { + __u8 gain_and_invert[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_ALIGNED_INPUT_COUNT]; + __u8 flag[SNDRV_FIREWIRE_MOTU_REGISTER_DSP_ALIGNED_INPUT_COUNT]; + } input; + __u8 reserved[64]; +}; + +/* + * In below MOTU models, software is allowed to control their DSP by command in frame of + * asynchronous transaction to 0x'ffff'0001'0000: + * + * - 828 mk3 (FireWire only and Hybrid) + * - 896 mk3 (FireWire only and Hybrid) + * - Ultralite mk3 (FireWire only and Hybrid) + * - Traveler mk3 + * - Track 16 + * + * On the other hand, the states of hardware meter is split into specific messages included in the + * sequence of isochronous packet. ALSA firewire-motu driver gathers the message and allow userspace + * application to read it via ioctl. + */ + +#define SNDRV_FIREWIRE_MOTU_COMMAND_DSP_METER_COUNT 400 + +/** + * struct snd_firewire_motu_command_dsp_meter - the container for meter information in DSP + * controlled by command + * @data: Signal level meters. The mapping between position and signal channel is model-dependent. + * + * The structure expresses the part of DSP status for hardware meter. The 32 bit storage is + * estimated to include IEEE 764 32 bit single precision floating point (binary32) value. It is + * expected to be linear value (not logarithm) for audio signal level between 0.0 and +1.0. + */ +struct snd_firewire_motu_command_dsp_meter { +#ifdef __KERNEL__ + __u32 data[SNDRV_FIREWIRE_MOTU_COMMAND_DSP_METER_COUNT]; +#else + float data[SNDRV_FIREWIRE_MOTU_COMMAND_DSP_METER_COUNT]; +#endif +}; + #endif /* _UAPI_SOUND_FIREWIRE_H_INCLUDED */ diff --git a/include/uapi/sound/snd_ar_tokens.h b/include/uapi/sound/snd_ar_tokens.h new file mode 100644 index 000000000000..440c0725660b --- /dev/null +++ b/include/uapi/sound/snd_ar_tokens.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +#ifndef __SND_AR_TOKENS_H__ +#define __SND_AR_TOKENS_H__ + +#define APM_SUB_GRAPH_PERF_MODE_LOW_POWER 0x1 +#define APM_SUB_GRAPH_PERF_MODE_LOW_LATENCY 0x2 + +#define APM_SUB_GRAPH_DIRECTION_TX 0x1 +#define APM_SUB_GRAPH_DIRECTION_RX 0x2 + +/** Scenario ID Audio Playback */ +#define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1 +/* Scenario ID Audio Record */ +#define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2 +/* Scenario ID Voice call. */ +#define APM_SUB_GRAPH_SID_VOICE_CALL 0x3 + +/* container capability ID Pre/Post Processing (PP) */ +#define APM_CONTAINER_CAP_ID_PP 0x1 +/* container capability ID Compression/Decompression (CD) */ +#define APM_CONTAINER_CAP_ID_CD 0x2 +/* container capability ID End Point(EP) */ +#define APM_CONTAINER_CAP_ID_EP 0x3 +/* container capability ID Offload (OLC) */ +#define APM_CONTAINER_CAP_ID_OLC 0x4 + +/* container graph position Stream */ +#define APM_CONT_GRAPH_POS_STREAM 0x1 +/* container graph position Per Stream Per Device*/ +#define APM_CONT_GRAPH_POS_PER_STR_PER_DEV 0x2 +/* container graph position Stream-Device */ +#define APM_CONT_GRAPH_POS_STR_DEV 0x3 +/* container graph position Global Device */ +#define APM_CONT_GRAPH_POS_GLOBAL_DEV 0x4 + +#define APM_PROC_DOMAIN_ID_MDSP 0x1 +#define APM_PROC_DOMAIN_ID_ADSP 0x2 +#define APM_PROC_DOMAIN_ID_SDSP 0x4 +#define APM_PROC_DOMAIN_ID_CDSP 0x5 + +#define PCM_INTERLEAVED 1 +#define PCM_DEINTERLEAVED_PACKED 2 +#define PCM_DEINTERLEAVED_UNPACKED 3 +#define AR_I2S_WS_SRC_EXTERNAL 0 +#define AR_I2S_WS_SRC_INTERNAL 1 + +enum ar_event_types { + AR_EVENT_NONE = 0, + AR_PGA_DAPM_EVENT +}; + +/* + * Kcontrol IDs + */ +#define SND_SOC_AR_TPLG_FE_BE_GRAPH_CTL_MIX 256 +#define SND_SOC_AR_TPLG_VOL_CTL 257 + +/** + * %AR_TKN_U32_SUB_GRAPH_INSTANCE_ID: Sub Graph Instance Id + * + * %AR_TKN_U32_SUB_GRAPH_PERF_MODE: Performance mode of subgraph + * APM_SUB_GRAPH_PERF_MODE_LOW_POWER = 1, + * APM_SUB_GRAPH_PERF_MODE_LOW_LATENCY = 2 + * + * %AR_TKN_U32_SUB_GRAPH_DIRECTION: Direction of subgraph + * APM_SUB_GRAPH_DIRECTION_TX = 1, + * APM_SUB_GRAPH_DIRECTION_RX = 2 + * + * %AR_TKN_U32_SUB_GRAPH_SCENARIO_ID: Scenario ID for subgraph + * APM_SUB_GRAPH_SID_AUDIO_PLAYBACK = 1, + * APM_SUB_GRAPH_SID_AUDIO_RECORD = 2, + * APM_SUB_GRAPH_SID_VOICE_CALL = 3 + * + * %AR_TKN_U32_CONTAINER_INSTANCE_ID: Container Instance ID + * + * %AR_TKN_U32_CONTAINER_CAPABILITY_ID: Container capability ID + * APM_CONTAINER_CAP_ID_PP = 1, + * APM_CONTAINER_CAP_ID_CD = 2, + * APM_CONTAINER_CAP_ID_EP = 3, + * APM_CONTAINER_CAP_ID_OLC = 4 + * + * %AR_TKN_U32_CONTAINER_STACK_SIZE: Stack size in the container. + * + * %AR_TKN_U32_CONTAINER_GRAPH_POS: Graph Position + * APM_CONT_GRAPH_POS_STREAM = 1, + * APM_CONT_GRAPH_POS_PER_STR_PER_DEV = 2, + * APM_CONT_GRAPH_POS_STR_DEV = 3, + * APM_CONT_GRAPH_POS_GLOBAL_DEV = 4 + * + * %AR_TKN_U32_CONTAINER_PROC_DOMAIN: Processor domain of container + * APM_PROC_DOMAIN_ID_MDSP = 1, + * APM_PROC_DOMAIN_ID_ADSP = 2, + * APM_PROC_DOMAIN_ID_SDSP = 4, + * APM_PROC_DOMAIN_ID_CDSP = 5 + * + * %AR_TKN_U32_MODULE_ID: Module ID + * + * %AR_TKN_U32_MODULE_INSTANCE_ID: Module Instance ID. + * + * %AR_TKN_U32_MODULE_MAX_IP_PORTS: Module maximum input ports + * + * %AR_TKN_U32_MODULE_MAX_OP_PORTS: Module maximum output ports. + * + * %AR_TKN_U32_MODULE_IN_PORTS: Number of in ports + * + * %AR_TKN_U32_MODULE_OUT_PORTS: Number of out ports. + * + * %AR_TKN_U32_MODULE_SRC_OP_PORT_ID: Source module output port ID + * + * %AR_TKN_U32_MODULE_DST_IN_PORT_ID: Destination module input port ID + * + * %AR_TKN_U32_MODULE_HW_IF_IDX: Interface index types for I2S/LPAIF + * + * %AR_TKN_U32_MODULE_HW_IF_TYPE: Interface type + * LPAIF = 0, + * LPAIF_RXTX = 1, + * LPAIF_WSA = 2, + * LPAIF_VA = 3, + * LPAIF_AXI = 4 + * + * %AR_TKN_U32_MODULE_FMT_INTERLEAVE: PCM Interleaving + * PCM_INTERLEAVED = 1, + * PCM_DEINTERLEAVED_PACKED = 2, + * PCM_DEINTERLEAVED_UNPACKED = 3 + * + * %AR_TKN_U32_MODULE_FMT_DATA: data format + * FIXED POINT = 1, + * IEC60958 PACKETIZED = 3, + * IEC60958 PACKETIZED NON LINEAR = 8, + * COMPR OVER PCM PACKETIZED = 7, + * IEC61937 PACKETIZED = 2, + * GENERIC COMPRESSED = 5 + * + * %AR_TKN_U32_MODULE_FMT_SAMPLE_RATE: sample rate + * + * %AR_TKN_U32_MODULE_FMT_BIT_DEPTH: bit depth + * + * %AR_TKN_U32_MODULE_SD_LINE_IDX: I2S serial data line idx + * I2S_SD0 = 1, + * I2S_SD1 = 2, + * I2S_SD2 = 3, + * I2S_SD3 = 4, + * I2S_QUAD01 = 5, + * I2S_QUAD23 = 6, + * I2S_6CHS = 7, + * I2S_8CHS = 8 + * + * %AR_TKN_U32_MODULE_WS_SRC: Word Select Source + * AR_I2S_WS_SRC_EXTERNAL = 0, + * AR_I2S_WS_SRC_INTERNAL = 1, + * + * %AR_TKN_U32_MODULE_FRAME_SZ_FACTOR: Frame size factor + * + * %AR_TKN_U32_MODULE_LOG_CODE: Log Module Code + * + * %AR_TKN_U32_MODULE_LOG_TAP_POINT_ID: logging tap point of this module + * + * %AR_TKN_U32_MODULE_LOG_MODE: logging mode + * LOG_WAIT = 0, + * LOG_IMMEDIATELY = 1 + * + * %AR_TKN_DAI_INDEX: dai index + * + */ + +/* DAI Tokens */ +#define AR_TKN_DAI_INDEX 1 +/* SUB GRAPH Tokens */ +#define AR_TKN_U32_SUB_GRAPH_INSTANCE_ID 2 +#define AR_TKN_U32_SUB_GRAPH_PERF_MODE 3 +#define AR_TKN_U32_SUB_GRAPH_DIRECTION 4 +#define AR_TKN_U32_SUB_GRAPH_SCENARIO_ID 5 + +/* Container Tokens */ +#define AR_TKN_U32_CONTAINER_INSTANCE_ID 100 +#define AR_TKN_U32_CONTAINER_CAPABILITY_ID 101 +#define AR_TKN_U32_CONTAINER_STACK_SIZE 102 +#define AR_TKN_U32_CONTAINER_GRAPH_POS 103 +#define AR_TKN_U32_CONTAINER_PROC_DOMAIN 104 + +/* Module Tokens */ +#define AR_TKN_U32_MODULE_ID 200 +#define AR_TKN_U32_MODULE_INSTANCE_ID 201 +#define AR_TKN_U32_MODULE_MAX_IP_PORTS 202 +#define AR_TKN_U32_MODULE_MAX_OP_PORTS 203 +#define AR_TKN_U32_MODULE_IN_PORTS 204 +#define AR_TKN_U32_MODULE_OUT_PORTS 205 +#define AR_TKN_U32_MODULE_SRC_OP_PORT_ID 206 +#define AR_TKN_U32_MODULE_DST_IN_PORT_ID 207 +#define AR_TKN_U32_MODULE_SRC_INSTANCE_ID 208 +#define AR_TKN_U32_MODULE_DST_INSTANCE_ID 209 + + +#define AR_TKN_U32_MODULE_HW_IF_IDX 250 +#define AR_TKN_U32_MODULE_HW_IF_TYPE 251 +#define AR_TKN_U32_MODULE_FMT_INTERLEAVE 252 +#define AR_TKN_U32_MODULE_FMT_DATA 253 +#define AR_TKN_U32_MODULE_FMT_SAMPLE_RATE 254 +#define AR_TKN_U32_MODULE_FMT_BIT_DEPTH 255 +#define AR_TKN_U32_MODULE_SD_LINE_IDX 256 +#define AR_TKN_U32_MODULE_WS_SRC 257 +#define AR_TKN_U32_MODULE_FRAME_SZ_FACTOR 258 +#define AR_TKN_U32_MODULE_LOG_CODE 259 +#define AR_TKN_U32_MODULE_LOG_TAP_POINT_ID 260 +#define AR_TKN_U32_MODULE_LOG_MODE 261 + +#endif /* __SND_AR_TOKENS_H__ */ diff --git a/include/uapi/sound/sof/tokens.h b/include/uapi/sound/sof/tokens.h index a642bf30c027..02b71a8deea4 100644 --- a/include/uapi/sound/sof/tokens.h +++ b/include/uapi/sound/sof/tokens.h @@ -51,6 +51,7 @@ #define SOF_TKN_SCHED_CORE 203 #define SOF_TKN_SCHED_FRAMES 204 #define SOF_TKN_SCHED_TIME_DOMAIN 205 +#define SOF_TKN_SCHED_DYNAMIC_PIPELINE 206 /* volume */ #define SOF_TKN_VOLUME_RAMP_STEP_TYPE 250 |