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authorBiju Das <biju.das.jz@bp.renesas.com>2022-09-19 09:41:10 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2022-10-17 10:03:59 +0200
commit1625fbc1f73f1fa8f77c38ea554cc0b2327b156b (patch)
tree6e11e2a3a9f35cae2b74232a62daae1889cb32ba /init
parent9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff)
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clk: renesas: rzg2l: Support sd clk mux round operation
Currently, determine_rate() is not doing any round operation and due to this it always selects a lower clock source compared to the closest higher one. Support sd clk mux round operation by passing CLK_MUX_ROUND_CLOSEST flag to clk_mux_determine_rate_flags(). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220919084110.3065156-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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