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authorPalmer Dabbelt <palmer@rivosinc.com>2024-04-09 11:39:46 -0700
committerPalmer Dabbelt <palmer@rivosinc.com>2024-04-28 14:50:35 -0700
commitd4b500cceb0e09ae22722d41454df6012848062b (patch)
treecc21e08f50258392f59313345a7127938079f7a8 /io_uring/register.h
parent70a57b247251aabadd67795c3097c0fcc616e533 (diff)
parentf862bbf4cdca696ef3073c5cf3d340b778a3e42a (diff)
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Merge patch series "riscv: 64-bit NOMMU fixes and enhancements"
Samuel Holland <samuel.holland@sifive.com> says: This series aims to improve support for NOMMU, specifically by making it easier to test NOMMU kernels in QEMU and on various widely-available hardware (errata permitting). After all, everything supports Svbare... After applying this series, a NOMMU kernel based on defconfig (changing only the three options below*) boots to userspace on QEMU when passed as -kernel. # CONFIG_RISCV_M_MODE is not set # CONFIG_MMU is not set CONFIG_NONPORTABLE=y *if you are using LLD, you must also disable BPF_SYSCALL and KALLSYMS, because LLD bails on out-of-range references to undefined weak symbols. * b4-shazam-merge: riscv: Allow NOMMU kernels to run in S-mode riscv: Remove MMU dependency from Zbb and Zicboz riscv: Fix loading 64-bit NOMMU kernels past the start of RAM riscv: Fix TASK_SIZE on 64-bit NOMMU Link: https://lore.kernel.org/r/20240227003630.3634533-1-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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