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| author | Zhang Rui <rui.zhang@intel.com> | 2022-08-18 21:21:46 +0800 |
|---|---|---|
| committer | Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> | 2023-03-22 13:36:55 -0700 |
| commit | c5a295caefa33ce7599d7afbe7a2e9b1bc8d92a2 (patch) | |
| tree | 1719bcf36c07728b8d6fe811ae922a1a2ef08881 /lib/digsig.c | |
| parent | b1e9b87b3b5999786685eb882afb99c468af94c1 (diff) | |
| download | linux-stable-c5a295caefa33ce7599d7afbe7a2e9b1bc8d92a2.tar.gz linux-stable-c5a295caefa33ce7599d7afbe7a2e9b1bc8d92a2.tar.bz2 linux-stable-c5a295caefa33ce7599d7afbe7a2e9b1bc8d92a2.zip | |
tools/power/x86/intel-speed-select: Hide invalid TRL level
TRL levels with Zero ratio values is meaningless.
Prevent these TRL levels from being displayed.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Diffstat (limited to 'lib/digsig.c')
0 files changed, 0 insertions, 0 deletions