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author | Anthony Koo <Anthony.Koo@amd.com> | 2019-01-20 01:08:02 -0500 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2019-02-06 13:30:44 -0500 |
commit | 68f1a00c23d443c9d940fbd512a195e9e6c08b11 (patch) | |
tree | dafcbc81858c8faa6c77d5c1c61beec8e620d551 /lib/libcrc32c.c | |
parent | c00800c46e832ca27f4db489b8c28a56603f8d2c (diff) | |
download | linux-stable-68f1a00c23d443c9d940fbd512a195e9e6c08b11.tar.gz linux-stable-68f1a00c23d443c9d940fbd512a195e9e6c08b11.tar.bz2 linux-stable-68f1a00c23d443c9d940fbd512a195e9e6c08b11.zip |
drm/amd/display: interface to check if timing can be seamless
[Why]
Need to figure out whether a timing we want to commit matches
something that GOP already programmed, in which case
we can decide to some optimizations
[How]
1. Add way to check for DIG FE
2. Add way to check for matching OTG timing
3. Add way to check for matching pixel clock (if possible)
- Currently only support DP for pixel clock, since it is easy to calc
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'lib/libcrc32c.c')
0 files changed, 0 insertions, 0 deletions