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| author | Thomas Gleixner <tglx@linutronix.de> | 2019-03-21 12:30:54 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2019-03-21 12:30:54 +0100 |
| commit | 3ce8461f45a7486b286afa2ae5619ce6aed8b6db (patch) | |
| tree | cc445fa3aed0f434bde55320080d8e4969066a5d /net/sched/cls_u32.c | |
| parent | 551417af91b163bd697eb50b3601adae2177c28a (diff) | |
| parent | fca269f201a8d9985c0a31fb60b15d4eb57cef80 (diff) | |
| download | linux-stable-3ce8461f45a7486b286afa2ae5619ce6aed8b6db.tar.gz linux-stable-3ce8461f45a7486b286afa2ae5619ce6aed8b6db.tar.bz2 linux-stable-3ce8461f45a7486b286afa2ae5619ce6aed8b6db.zip | |
Merge tag 'irqchip-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Pull irqchip updates for 5.1 from Marc Zyngier:
- irqsteer error handling fix
- GICv3 range coalescing fix
- stm32 coprocessor coexistence fixes
- mbigen MSI teardown fix
- non-DT secondary GIC infrastructure removed
- various cleanups (brcmstb-l2, mmp)
- new DT bindings (r8a774c0)
Diffstat (limited to 'net/sched/cls_u32.c')
0 files changed, 0 insertions, 0 deletions