spi: cadence-qspi: revert "Improve spi memory performance"

During the v6.14-rc cycles, there has been an issue with syscons which
prevented TI chipid controller to probe, itself preventing the only DMA
engine on AM62A with the memcpy capability to probe, which is needed for
the SPI controller to work in its most efficient configuration.

The SPI controller on AM62A can be used in DAC and INDAC mode, which are
some kind of direct mapping vs. CPU-controlled SPI operations,
respectively. However, because of hardware constraints (some kind of
request line not being driven), INDAC mode cannot leverage DMA without
risking to underflow the SPI FIFO. This mode costs a lot of CPU
cycles. On the other side however, DAC mode can be used with and without
DMA support, but in practice, DMA transfers are way more efficient
because of the burst capabilities that the CPU does not have.

As a result, in terms of read throughput, using a Winbond chip in 1-8-8
SDR mode, we get:
- 3.5MiB/s in DAC mode without DMA
- 9.0MiB/s in INDAC mode (CPU more busy)
- a fluctuating 9 to 12MiB/s in DAC mode with DMA (a constant 14.5MiB/s
  without CPUfreq)

The reason for the patch that is being reverted is that because of the
syscon issue, we were using a very un-efficient DAC configuration (no
DMA), but since:

commit 5728c92ae112 ("mfd: syscon: Restore device_node_to_regmap() for non-syscon nodes")

the probing of the DMA controller has been fixed, and the performances are
back to normal, so we can safely revert this commit.

This is a revert of:
commit cce2200dacd6 ("spi: cadence-qspi: Improve spi memory performance")

Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20250401134748.242846-1-miquel.raynal@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>

0 files changed, 0 insertions, 0 deletions