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| author | Thierry Reding <treding@nvidia.com> | 2016-02-05 17:17:32 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-06-10 16:11:44 +0200 |
| commit | eddb65e7fdeac175cd61c54da5a217f47861ddd2 (patch) | |
| tree | 163488134796b1dd5b835776572ec07c3e416fb5 /scripts/gdb/linux/utils.py | |
| parent | 1a695a905c18548062509178b98bc91e67510864 (diff) | |
| download | linux-stable-eddb65e7fdeac175cd61c54da5a217f47861ddd2.tar.gz linux-stable-eddb65e7fdeac175cd61c54da5a217f47861ddd2.tar.bz2 linux-stable-eddb65e7fdeac175cd61c54da5a217f47861ddd2.zip | |
clk: tegra: Fixup post dividers on Tegra210
Commit 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and
_calc_dynamic_ramp_rate") changed the PLL divider computation logic to
consistently use P-divider values from tables as real dividers rather
than the hardware values. Unfortunately for some reason many of the
Tegra210 clocks didn't have their tables updated (most likely an over-
sight by me when applying the patches). This commit fixes them all up.
Cc: Jon Hunter <jonathanh@nvidia.com>
Cc: Rhyland Klein <rklein@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions