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author | Maciej W. Rozycki <macro@orcam.me.uk> | 2022-03-31 08:10:46 +0100 |
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committer | Thomas Gleixner <tglx@linutronix.de> | 2022-04-10 12:48:14 +0200 |
commit | fe62bc23620fa027162e05594a610ff5e556496a (patch) | |
tree | 33307813d2d594ecafed3539f54dfa4d0949d776 /sound/hda/ext | |
parent | 5a0e5fa957db79177baa851d687b6f6aa5a0be96 (diff) | |
download | linux-stable-fe62bc23620fa027162e05594a610ff5e556496a.tar.gz linux-stable-fe62bc23620fa027162e05594a610ff5e556496a.tar.bz2 linux-stable-fe62bc23620fa027162e05594a610ff5e556496a.zip |
x86/PCI: Add support for the SiS85C497 PIRQ router
The SiS 85C496/497 486 Green PC VESA/ISA/PCI Chipset has support for PCI
steering and the ELCR register implemented. These features are handled
by the SiS85C497 AT Bus Controller & Megacell (ATM) ISA bridge, however
the device is wired as a peer bridge directly to the host bus and has
its PCI configuration registers decoded at addresses 0x80-0xff by the
accompanying SiS85C496 PCI & CPU Memory Controller (PCM) host bridge[1].
Therefore we need to match on the host bridge's vendor and device ID.
Like with the SiS85C503 PIRQ router handle link value ranges of 1-4 and
0xc0-0xc3, corresponding respectively to PIRQ line numbers counted from
1 and link register PCI configuration space addresses.
References:
[1] "486 Green PC VESA/ISA/PCI Chipset, SiS 85C496/497", Rev 3.0,
Silicon Integrated Systems Corp., July 1995, Part IV, Section 3.
"PCI Configuration Space Registers (00h ~ FFh)", p. 114
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Nikolai Zhubr <zhubr.2@gmail.com>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2203301610490.22465@angie.orcam.me.uk
Diffstat (limited to 'sound/hda/ext')
0 files changed, 0 insertions, 0 deletions