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| author | Venkata Prasad Potturu <venkataprasad.potturu@amd.com> | 2023-08-09 18:05:20 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-08-21 16:05:47 +0100 |
| commit | d0dab6b76a9f05bd25d7ad957c3275a9dec42a06 (patch) | |
| tree | f51b4ac9158816ad402f14e9352f488e30dd3de6 /sound/soc/sof/amd/acp-dsp-offset.h | |
| parent | 919a4a941863c539e982d34903e93d9777316f7d (diff) | |
| download | linux-stable-d0dab6b76a9f05bd25d7ad957c3275a9dec42a06.tar.gz linux-stable-d0dab6b76a9f05bd25d7ad957c3275a9dec42a06.tar.bz2 linux-stable-d0dab6b76a9f05bd25d7ad957c3275a9dec42a06.zip | |
ASoC: SOF: amd: Add sof support for vangogh platform
Add pci driver and platform driver to enable SOF support
on ACP5x architecture based Vangogh platform.
Signed-off-by: Venkata Prasad Potturu <venkataprasad.potturu@amd.com>
Link: https://lore.kernel.org/r/20230809123534.287707-1-venkataprasad.potturu@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/sof/amd/acp-dsp-offset.h')
| -rw-r--r-- | sound/soc/sof/amd/acp-dsp-offset.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/sound/soc/sof/amd/acp-dsp-offset.h b/sound/soc/sof/amd/acp-dsp-offset.h index 920155dee819..19ef2b4c46d6 100644 --- a/sound/soc/sof/amd/acp-dsp-offset.h +++ b/sound/soc/sof/amd/acp-dsp-offset.h @@ -3,7 +3,7 @@ * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * - * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. + * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. * * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> */ @@ -49,27 +49,33 @@ #define ACP_CONTROL 0x1004 #define ACP3X_I2S_PIN_CONFIG 0x1400 +#define ACP5X_I2S_PIN_CONFIG 0x1400 #define ACP6X_I2S_PIN_CONFIG 0x1440 /* Registers offsets from ACP_PGFSM block */ #define ACP3X_PGFSM_BASE 0x141C +#define ACP5X_PGFSM_BASE 0x1424 #define ACP6X_PGFSM_BASE 0x1024 #define PGFSM_CONTROL_OFFSET 0x0 #define PGFSM_STATUS_OFFSET 0x4 #define ACP3X_CLKMUX_SEL 0x1424 +#define ACP5X_CLKMUX_SEL 0x142C #define ACP6X_CLKMUX_SEL 0x102C /* Registers from ACP_INTR block */ #define ACP3X_EXT_INTR_STAT 0x1808 +#define ACP5X_EXT_INTR_STAT 0x1808 #define ACP6X_EXT_INTR_STAT 0x1A0C #define ACP3X_DSP_SW_INTR_BASE 0x1814 +#define ACP5X_DSP_SW_INTR_BASE 0x1814 #define ACP6X_DSP_SW_INTR_BASE 0x1808 #define DSP_SW_INTR_CNTL_OFFSET 0x0 #define DSP_SW_INTR_STAT_OFFSET 0x4 #define DSP_SW_INTR_TRIG_OFFSET 0x8 #define ACP_ERROR_STATUS 0x18C4 #define ACP3X_AXI2DAGB_SEM_0 0x1880 +#define ACP5X_AXI2DAGB_SEM_0 0x1884 #define ACP6X_AXI2DAGB_SEM_0 0x1874 /* Registers from ACP_SHA block */ |