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| author | Michal Simek <michal.simek@xilinx.com> | 2017-02-14 17:40:21 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-08-21 13:52:49 +0200 |
| commit | 3c220bf420908319cc1dc0715eb822e6a7c663e3 (patch) | |
| tree | 8f0fc6f0f66d891592960dd6b50b6a538446360f /tools/build/Makefile | |
| parent | e5e6f6872c7a6e2b15295574ecab8391c03808cd (diff) | |
| download | linux-stable-3c220bf420908319cc1dc0715eb822e6a7c663e3.tar.gz linux-stable-3c220bf420908319cc1dc0715eb822e6a7c663e3.tar.bz2 linux-stable-3c220bf420908319cc1dc0715eb822e6a7c663e3.zip | |
arm: zynq: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'tools/build/Makefile')
0 files changed, 0 insertions, 0 deletions