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authorAdrian Hunter <adrian.hunter@intel.com>2020-04-29 18:07:50 +0300
committerArnaldo Carvalho de Melo <acme@redhat.com>2020-05-05 16:35:30 -0300
commit43358d9dfb250842383cddad816a7538548a5070 (patch)
tree79bb30fba6f2f6a52f5668728dccbe2b057aad97 /tools/perf/Documentation/itrace.txt
parentf0a0251cee800bf90cff92ecfaf4a4d4c9c493b2 (diff)
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perf intel-pt: Update documentation about itrace G and L options
Provide a little more information about the new G and L options, particularly the issue with large PEBs. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Link: http://lore.kernel.org/lkml/20200429150751.12570-9-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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diff --git a/tools/perf/Documentation/itrace.txt b/tools/perf/Documentation/itrace.txt
index 0326050beebd..271484754fee 100644
--- a/tools/perf/Documentation/itrace.txt
+++ b/tools/perf/Documentation/itrace.txt
@@ -33,6 +33,10 @@
Also the number of last branch entries (default 64, max. 1024) for
instructions or transactions events can be specified.
+ Similar to options g and l, size may also be specified for options G and L.
+ On x86, note that G and L work poorly when data has been recorded with
+ large PEBS. Refer linkperf:perf-intel-pt[1] man page for details.
+
It is also possible to skip events generated (instructions, branches, transactions,
ptwrite, power) at the beginning. This is useful to ignore initialization code.