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| author | Andrew Kilroy <andrew.kilroy@arm.com> | 2021-10-06 09:11:03 +0100 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2021-10-20 11:19:50 -0300 |
| commit | 25bc4793dc89b845be8c1f1f37c00ee315363ce4 (patch) | |
| tree | 123f9c8b2d94951e7a2fc078e2f5de80f9aed365 /tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json | |
| parent | b85a4d61d30226080ff6fec9ea4096d369fd6852 (diff) | |
| download | linux-stable-25bc4793dc89b845be8c1f1f37c00ee315363ce4.tar.gz linux-stable-25bc4793dc89b845be8c1f1f37c00ee315363ce4.tar.bz2 linux-stable-25bc4793dc89b845be8c1f1f37c00ee315363ce4.zip | |
perf vendor events: Syntax corrections in Neoverse N1 json
There are some syntactical mistakes in the json files for the Cortex A76
N1 (Neoverse N1). This was obstructing parsing from an external tool.
This patch fixes the erroneous placement of commas causing the problems.
Reviewed-by: John Garry <john.garry@huawei.com>
Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20211006081106.8649-1-andrew.kilroy@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json index 8e59566cba8b..b0b439a36ae9 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json @@ -1,32 +1,32 @@ [ { - "ArchStdEvent": "SW_INCR", + "ArchStdEvent": "SW_INCR" }, { "PublicDescription": "This event counts all retired instructions, including those that fail their condition check.", - "ArchStdEvent": "INST_RETIRED", + "ArchStdEvent": "INST_RETIRED" }, { - "ArchStdEvent": "EXC_RETURN", + "ArchStdEvent": "EXC_RETURN" }, { "PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.", - "ArchStdEvent": "CID_WRITE_RETIRED", + "ArchStdEvent": "CID_WRITE_RETIRED" }, { - "ArchStdEvent": "INST_SPEC", + "ArchStdEvent": "INST_SPEC" }, { "PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.", - "ArchStdEvent": "TTBR_WRITE_RETIRED", + "ArchStdEvent": "TTBR_WRITE_RETIRED" }, - {, + { "PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches.", - "ArchStdEvent": "BR_RETIRED", + "ArchStdEvent": "BR_RETIRED" }, { "PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush.", - "ArchStdEvent": "BR_MIS_PRED_RETIRED", + "ArchStdEvent": "BR_MIS_PRED_RETIRED" }, { "ArchStdEvent": "ASE_SPEC" |