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| author | Shyam Sundar S K <Shyam-sundar.S-k@amd.com> | 2024-11-14 16:32:39 +0530 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2024-11-18 14:27:29 +0100 |
| commit | 473d0cb485876b29b71da34a0ea4b36e496cb1ea (patch) | |
| tree | 83c88f17ada29d8910d9e3ce239b128c4664702c /tools/perf/scripts/python/stackcollapse.py | |
| parent | 0a0d851ce1bc3f0dc0cdfc429c3b0a9ed6e9272e (diff) | |
| download | linux-stable-473d0cb485876b29b71da34a0ea4b36e496cb1ea.tar.gz linux-stable-473d0cb485876b29b71da34a0ea4b36e496cb1ea.tar.bz2 linux-stable-473d0cb485876b29b71da34a0ea4b36e496cb1ea.zip | |
i3c: dw: Add quirk to address OD/PP timing issue on AMD platform
The AMD Legacy I3C is having a problem with its IP, specifically with the
push-pull and open-drain pull-up registers. These registers need to be
manually programmed for every CCC submission to align with the duty cycle.
Therefore, add a quirk to address this issue.
Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20241114110239.660551-3-Shyam-sundar.S-k@amd.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions