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| author | Bjorn Helgaas <bhelgaas@google.com> | 2017-09-05 12:58:03 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-09-07 08:52:43 -0500 |
| commit | 582ffae852400264b189da7dca9a5212dd3dab01 (patch) | |
| tree | 3afb28f05a2e8e99e39bae7dc0d21a8d0ab87441 /tools/perf/scripts/python/stackcollapse.py | |
| parent | c7aca96aa48d59b08763452cf1881b7411876c59 (diff) | |
| download | linux-stable-582ffae852400264b189da7dca9a5212dd3dab01.tar.gz linux-stable-582ffae852400264b189da7dca9a5212dd3dab01.tar.bz2 linux-stable-582ffae852400264b189da7dca9a5212dd3dab01.zip | |
PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset
Apparently the PCIe capability is at address 0x40 in config space of X-Gene
v1 Root Ports. Add a definition of that and use the generic PCI_EXP_RTCTL
offset into the capability. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions