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authorZhang Rui <rui.zhang@intel.com>2023-04-22 11:59:04 +0800
committerZhang Rui <rui.zhang@intel.com>2023-09-27 22:14:19 +0800
commit6d35b8c4a661c849361239fe316035ea952606a3 (patch)
tree725032943d30ca58a256bd287e0481ae992924d8 /tools/power
parente338831b14d2da921348c8c4055b9f2c94effe73 (diff)
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tools/power/turbostat: Abstract RAPL divisor support
INTEL_FAM6_ATOM_SILVERMONT model needs a divisor to convert the raw Energy Units value from MSR_RAPL_POWER_UNIT. Abstract the support for RAPL divisor. Delete CPU model check in rapl_probe_intel(). Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools/power')
-rw-r--r--tools/power/x86/turbostat/turbostat.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 6314c40dc15b..a31724335671 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -289,6 +289,7 @@ struct platform_features {
int plr_msrs; /* MSR_CORE/GFX/RING_PERF_LIMIT_REASONS */
int rapl_msrs; /* RAPL PKG/DRAM/CORE/GFX MSRs, AMD RAPL MSRs */
bool has_per_core_rapl; /* Indicates cores energy collection is per-core, not per-package. AMD specific for now */
+ bool has_rapl_divisor; /* Divisor for Energy unit raw value from MSR_RAPL_POWER_UNIT */
int tcc_offset_bits; /* TCC Offset bits in MSR_IA32_TEMPERATURE_TARGET */
};
@@ -595,6 +596,7 @@ static const struct platform_features slv_features = {
.cst_limit = CST_LIMIT_SLV,
.trl_msrs = TRL_ATOM,
.rapl_msrs = RAPL_PKG | RAPL_CORE,
+ .has_rapl_divisor = 1,
};
static const struct platform_features slvd_features = {
@@ -4865,7 +4867,7 @@ void rapl_probe_intel(unsigned int model)
return;
rapl_power_units = 1.0 / (1 << (msr & 0xF));
- if (model == INTEL_FAM6_ATOM_SILVERMONT)
+ if (platform->has_rapl_divisor)
rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
else
rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));