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| author | Dan Williams <dan.j.williams@intel.com> | 2022-05-18 16:34:54 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 08:50:41 -0700 |
| commit | dd2d42ad6f422076d1bd49b132bec74376c26f5c (patch) | |
| tree | 1c227dbf211e9c9ab805e8129c5955713a7ac5a9 /tools/testing/cxl | |
| parent | 14d78874077442d1d0f08129f5a0ea5070984b4b (diff) | |
| download | linux-stable-dd2d42ad6f422076d1bd49b132bec74376c26f5c.tar.gz linux-stable-dd2d42ad6f422076d1bd49b132bec74376c26f5c.tar.bz2 linux-stable-dd2d42ad6f422076d1bd49b132bec74376c26f5c.zip | |
cxl/mem: Skip range enumeration if mem_enable clear
When a device does not have mem_enable set then the current range
settings are moot. Skip the enumeration and cause cxl_hdm_decode_init()
to proceed directly to enable the HDM Decoder Capability.
Fixes: 560f78559006 ("cxl/pci: Retrieve CXL DVSEC memory info")
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291689442.1426646.18012291761753694336.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/testing/cxl')
0 files changed, 0 insertions, 0 deletions