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| author | Eric Auger <eric.auger@redhat.com> | 2020-01-24 15:25:32 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-02-14 16:33:26 -0500 |
| commit | b818a55bc4e8f9598c0ea9fd3848e58f74cf0686 (patch) | |
| tree | b7fb1204ebdaa2a9f9f3eadb61a3b92a4ea4cd00 /virt/kvm | |
| parent | f8d4dfffbb4a3e3f8fcc97a1cfe6797b39cc053b (diff) | |
| download | linux-stable-b818a55bc4e8f9598c0ea9fd3848e58f74cf0686.tar.gz linux-stable-b818a55bc4e8f9598c0ea9fd3848e58f74cf0686.tar.bz2 linux-stable-b818a55bc4e8f9598c0ea9fd3848e58f74cf0686.zip | |
KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset
commit 3837407c1aa1101ed5e214c7d6041e7a23335c6e upstream.
The specification says PMSWINC increments PMEVCNTR<n>_EL1 by 1
if PMEVCNTR<n>_EL0 is enabled and configured to count SW_INCR.
For PMEVCNTR<n>_EL0 to be enabled, we need both PMCNTENSET to
be set for the corresponding event counter but we also need
the PMCR.E bit to be set.
Fixes: 7a0adc7064b8 ("arm64: KVM: Add access handler for PMSWINC register")
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200124142535.29386-2-eric.auger@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'virt/kvm')
| -rw-r--r-- | virt/kvm/arm/pmu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 1c5b76c46e26..6d52fd50c1ff 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -316,6 +316,9 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) if (val == 0) return; + if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) + return; + enable = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++) { if (!(val & BIT(i))) |