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| author | Horia GeantA <horia.geanta@nxp.com> | 2023-04-05 11:07:52 +0200 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2023-04-14 18:59:34 +0800 |
| commit | 0489929f73a2b749cf409b95701bb6bd3c37cd91 (patch) | |
| tree | 1748e0e5e948ad09bd3e6950e92f921841459e6a /virt | |
| parent | ae1dd17daeb8193b1ea3665c89ade63cf7385182 (diff) | |
| download | linux-stable-0489929f73a2b749cf409b95701bb6bd3c37cd91.tar.gz linux-stable-0489929f73a2b749cf409b95701bb6bd3c37cd91.tar.bz2 linux-stable-0489929f73a2b749cf409b95701bb6bd3c37cd91.zip | |
crypto: caam - OP-TEE firmware support
caam driver needs to be aware of OP-TEE f/w presence, since some things
are done differently:
1. there is no access to controller's register page (note however that
some registers are aliased in job rings' register pages)
2 Due to this, MCFGR[PS] cannot be read and driver assumes
MCFGR[PS] = b'0 - engine using 32-bit address pointers.
This is in sync with the fact that:
-all i.MX SoCs currently use MCFGR[PS] = b'0
-only i.MX OP-TEE use cases don't allow access to controller register page
Signed-off-by: Horia GeantA <horia.geanta@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'virt')
0 files changed, 0 insertions, 0 deletions