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-rw-r--r--arch/m68k/include/asm/cacheflush_no.h40
-rw-r--r--arch/m68k/include/asm/m52xxacr.h27
-rw-r--r--arch/m68k/include/asm/m53xxacr.h18
-rw-r--r--arch/m68k/include/asm/m54xxacr.h11
-rw-r--r--arch/m68k/include/asm/mcfcache.h150
-rw-r--r--arch/m68knommu/platform/coldfire/head.S26
6 files changed, 80 insertions, 192 deletions
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 52b11ac9a30c..8ada4ffc98e5 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -2,7 +2,7 @@
#define _M68KNOMMU_CACHEFLUSH_H
/*
- * (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>
+ * (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com>
*/
#include <linux/mm.h>
#include <asm/mcfsim.h>
@@ -10,7 +10,7 @@
#define flush_cache_all() __flush_cache_all()
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) __flush_cache_all()
+#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr) do { } while (0)
#ifndef flush_dcache_range
#define flush_dcache_range(start,len) __flush_cache_all()
@@ -33,41 +33,13 @@
#ifndef __flush_cache_all
static inline void __flush_cache_all(void)
{
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
+#ifdef CACHE_INVALIDATE
__asm__ __volatile__ (
- "movel #0x81400110, %%d0\n\t"
+ "movel %0, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
- : : : "d0" );
-#endif /* CONFIG_M523x || CONFIG_M527x */
-#if defined(CONFIG_M528x)
- __asm__ __volatile__ (
- "movel #0x81000200, %%d0\n\t"
- "movec %%d0, %%CACR\n\t"
- "nop\n\t"
- : : : "d0" );
-#endif /* CONFIG_M528x */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
- __asm__ __volatile__ (
- "movel #0x81000100, %%d0\n\t"
- "movec %%d0, %%CACR\n\t"
- "nop\n\t"
- : : : "d0" );
-#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
-#ifdef CONFIG_M5249
- __asm__ __volatile__ (
- "movel #0xa1000200, %%d0\n\t"
- "movec %%d0, %%CACR\n\t"
- "nop\n\t"
- : : : "d0" );
-#endif /* CONFIG_M5249 */
-#ifdef CONFIG_M532x
- __asm__ __volatile__ (
- "movel #0x81000210, %%d0\n\t"
- "movec %%d0, %%CACR\n\t"
- "nop\n\t"
- : : : "d0" );
-#endif /* CONFIG_M532x */
+ : : "i" (CACHE_INVALIDATE) : "d0" );
+#endif
}
#endif /* __flush_cache_all */
diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h
index 4c92d999ee01..52230b5e1e4d 100644
--- a/arch/m68k/include/asm/m52xxacr.h
+++ b/arch/m68k/include/asm/m52xxacr.h
@@ -52,5 +52,32 @@
#define ACR_BWE 0x00000020 /* Write buffer enabled */
#define ACR_WPROTECT 0x00000004 /* Write protect region */
+/*
+ * Set the cache controller settings we will use. This code is set to
+ * only use the instruction cache, even on the controllers that support
+ * split cache. (This setup is trying to preserve the existing behavior
+ * for now, in the furture I hope to actually use the split cache mode).
+ */
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+ defined(CONFIG_M5249) || defined(CONFIG_M5272)
+#define CACHE_INIT (CACR_CINV)
+#define CACHE_MODE (CACR_CENB + CACR_DCM)
+#else
+#ifdef CONFIG_COLDFIRE_SW_A7
+#define CACHE_INIT (CACR_CINV + CACR_DISD)
+#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM)
+#else
+#define CACHE_INIT (CACR_CINV + CACR_DISD + CACR_EUSP)
+#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP)
+#endif
+#endif
+
+#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
+
+#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
+ (0x000f0000) + \
+ (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
+#define ACR1_MODE 0
+
/****************************************************************************/
#endif /* m52xxsim_h */
diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
index 532fbb91185f..74c81c9b177e 100644
--- a/arch/m68k/include/asm/m53xxacr.h
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -48,5 +48,23 @@
#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */
#define ACR_WPROTECT 0x00000004 /* Write protect region */
+/*
+ * Set the cache controller settings we will use. This default in the
+ * CACR is cache inhibited, we use the ACR register to set cacheing
+ * enabled on the regions we want (eg RAM).
+ */
+#ifdef CONFIG_COLDFIRE_SW_A7
+#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE)
+#else
+#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
+#endif
+
+#define CACHE_INIT CACR_CINVA
+
+#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
+ (0x000f0000) + \
+ (ACR_ENABLE + ACR_ANY + ACR_CM_CB))
+#define ACR1_MODE 0
+
/****************************************************************************/
#endif /* m53xxsim_h */
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 12209c68b904..3c81a7a34a8f 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -73,11 +73,16 @@
#else
#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
#endif
-
#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
-
#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
+#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
+#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
+#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE)
+#define ACR1_MODE 0
+#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE)
+#define ACR3_MODE 0
+
#ifndef __ASSEMBLY__
#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT)
@@ -112,7 +117,7 @@ static inline void __m54xx_flush_cache_all(void)
: "i" (CACHE_LINE_SIZE),
"i" (DCACHE_SIZE / CACHE_WAYS),
"i" (CACHE_WAYS),
- "i" (CACHE_MODE|CACR_DCINVA|CACR_BCINVA|CACR_ICINVA)
+ "i" (CACHE_INVALIDATE)
: "d0", "a0" );
}
diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h
deleted file mode 100644
index 2b3a6cfaaac0..000000000000
--- a/arch/m68k/include/asm/mcfcache.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/****************************************************************************/
-
-/*
- * mcfcache.h -- ColdFire CPU cache support code
- *
- * (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com>
- */
-
-/****************************************************************************/
-#ifndef __M68KNOMMU_MCFCACHE_H
-#define __M68KNOMMU_MCFCACHE_H
-/****************************************************************************/
-
-
-/*
- * The different ColdFire families have different cache arrangments.
- * Everything from a small instruction only cache, to configurable
- * data and/or instruction cache, to unified instruction/data, to
- * harvard style separate instruction and data caches.
- */
-
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
-/*
- * Simple version 2 core cache. These have instruction cache only,
- * we just need to invalidate it and enable it.
- */
-.macro CACHE_ENABLE
- movel #0x01000000,%d0 /* invalidate cache cmd */
- movec %d0,%CACR /* do invalidate cache */
- movel #0x80000100,%d0 /* setup cache mask */
- movec %d0,%CACR /* enable cache */
-.endm
-#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
-
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
-/*
- * New version 2 cores have a configurable split cache arrangement.
- * For now I am just enabling instruction cache - but ultimately I
- * think a split instruction/data cache would be better.
- */
-.macro CACHE_ENABLE
- movel #0x01400000,%d0
- movec %d0,%CACR /* invalidate cache */
- nop
- movel #0x0000c000,%d0 /* set SDRAM cached only */
- movec %d0,%ACR0
- movel #0x00000000,%d0 /* no other regions cached */
- movec %d0,%ACR1
- movel #0x80400110,%d0 /* configure cache */
- movec %d0,%CACR /* enable cache */
- nop
-.endm
-#endif /* CONFIG_M523x || CONFIG_M527x */
-
-#if defined(CONFIG_M528x)
-.macro CACHE_ENABLE
- nop
- movel #0x01000000, %d0
- movec %d0, %CACR /* Invalidate cache */
- nop
- movel #0x0000c020, %d0 /* Set SDRAM cached only */
- movec %d0, %ACR0
- movel #0x00000000, %d0 /* No other regions cached */
- movec %d0, %ACR1
- movel #0x80000200, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- nop
-.endm
-#endif /* CONFIG_M528x */
-
-#if defined(CONFIG_M5249) || defined(CONFIG_M5307)
-/*
- * The version 3 core cache. Oddly enough the version 2 core 5249
- * has the same SDRAM and cache setup as the version 3 cores.
- * This is a single unified instruction/data cache.
- */
-.macro CACHE_ENABLE
- movel #0x01000000,%d0 /* invalidate whole cache */
- movec %d0,%CACR
- nop
-#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3)
- movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
-#else
- movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */
-#endif
- movec %d0,%ACR0
- movel #0x00000000,%d0 /* no other regions cached */
- movec %d0,%ACR1
- movel #0xa0000200,%d0 /* enable cache */
- movec %d0,%CACR
- nop
-.endm
-#endif /* CONFIG_M5249 || CONFIG_M5307 */
-
-#if defined(CONFIG_M532x)
-.macro CACHE_ENABLE
- movel #0x01000000,%d0 /* invalidate cache cmd */
- movec %d0,%CACR /* do invalidate cache */
- nop
- movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */
- movec %d0,%ACR0
- movel #0x00000000,%d0 /* no other regions cached */
- movec %d0,%ACR1
- movel #0x80000210,%d0 /* setup cache mask */
- movec %d0,%CACR /* enable cache */
- nop
-.endm
-#endif /* CONFIG_M532x */
-
-#if defined(CONFIG_M5407) || defined(CONFIG_M54xx)
-
-.macro CACHE_ENABLE
- /* invalidate whole cache */
- movel #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0
- movec %d0,%CACR
- nop
- /* addresses range for data cache : 0x00000000-0x0fffffff */
- movel #(0x000f0000+DATA_CACHE_MODE),%d0 /* set SDRAM cached */
- movec %d0, %ACR0
- movel #0x00000000,%d0 /* no other regions cached */
- movec %d0, %ACR1
- /* addresses range for instruction cache : 0x00000000-0x0fffffff */
- movel #(0x000f0000+INSN_CACHE_MODE),%d0 /* set SDRAM cached */
- movec %d0, %ACR2
- movel #0x00000000,%d0 /* no other regions cached */
- movec %d0, %ACR3
- /* enable caches */
- movel #(CACHE_MODE),%d0
- movec %d0,%CACR
- nop
-.endm
-#endif /* CONFIG_M5407 || CONFIG_M54xx */
-
-#if defined(CONFIG_M520x)
-.macro CACHE_ENABLE
- move.l #0x01000000,%d0 /* invalidate whole cache */
- movec %d0,%CACR
- nop
- move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
- movec %d0,%ACR0
- move.l #0x00000000,%d0 /* no other regions cached */
- movec %d0,%ACR1
- move.l #0x80400010,%d0 /* enable 8K instruction cache */
- movec %d0,%CACR
- nop
-.endm
-#endif /* CONFIG_M520x */
-
-/****************************************************************************/
-#endif /* __M68KNOMMU_MCFCACHE_H */
diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S
index 0b2d7c7adf79..d5977909ae5f 100644
--- a/arch/m68knommu/platform/coldfire/head.S
+++ b/arch/m68knommu/platform/coldfire/head.S
@@ -3,7 +3,7 @@
/*
* head.S -- common startup code for ColdFire CPUs.
*
- * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>.
+ * (C) Copyright 1999-2010, Greg Ungerer <gerg@snapgear.com>.
*/
/*****************************************************************************/
@@ -13,7 +13,6 @@
#include <linux/init.h>
#include <asm/asm-offsets.h>
#include <asm/coldfire.h>
-#include <asm/mcfcache.h>
#include <asm/mcfsim.h>
#include <asm/thread_info.h>
@@ -173,10 +172,27 @@ _start:
/*
* Now that we know what the memory is, lets enable cache
- * and get things moving. This is Coldfire CPU specific.
+ * and get things moving. This is Coldfire CPU specific. Not
+ * all version cores have identical cache register setup. But
+ * it is very similar. Define the exact settings in the headers
+ * then the code here is the same for all.
*/
- CACHE_ENABLE /* enable CPU cache */
-
+ movel #CACHE_INIT,%d0 /* invalidate whole cache */
+ movec %d0,%CACR
+ nop
+ movel #ACR0_MODE,%d0 /* set RAM region for caching */
+ movec %d0,%ACR0
+ movel #ACR1_MODE,%d0 /* anything else to cache? */
+ movec %d0,%ACR1
+#ifdef ACR2_MODE
+ movel #ACR2_MODE,%d0
+ movec %d0,%ACR2
+ movel #ACR3_MODE,%d0
+ movec %d0,%ACR3
+#endif
+ movel #CACHE_MODE,%d0 /* enable cache */
+ movec %d0,%CACR
+ nop
#ifdef CONFIG_ROMFS_FS
/*
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 18:47:10 +0000