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12 files changed, 1297 insertions, 409 deletions
diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml index b3e9992525c2..907fb47cc84a 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml @@ -12,8 +12,8 @@ description: | and CEC. These DT bindings follow the Synopsys DWC HDMI TX bindings defined - in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with - the following device-specific properties. + in bridge/synopsys,dw-hdmi.yaml with the following device-specific + properties. maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt b/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt deleted file mode 100644 index 33bf981fbe33..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt +++ /dev/null @@ -1,33 +0,0 @@ -Synopsys DesignWare HDMI TX Encoder -=================================== - -This document defines device tree properties for the Synopsys DesignWare HDMI -TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding -specification by itself but is meant to be referenced by platform-specific -device tree bindings. - -When referenced from platform device tree bindings the properties defined in -this document are defined as follows. The platform device tree bindings are -responsible for defining whether each property is required or optional. - -- reg: Memory mapped base address and length of the DWC HDMI TX registers. - -- reg-io-width: Width of the registers specified by the reg property. The - value is expressed in bytes and must be equal to 1 or 4 if specified. The - register width defaults to 1 if the property is not present. - -- interrupts: Reference to the DWC HDMI TX interrupt. - -- clocks: References to all the clocks specified in the clock-names property - as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt. - -- clock-names: The DWC HDMI TX uses the following clocks. - - - "iahb" is the bus clock for either AHB and APB (mandatory). - - "isfr" is the internal register configuration clock (mandatory). - - "cec" is the HDMI CEC controller main clock (optional). - -- ports: The connectivity of the DWC HDMI TX with the rest of the system is - expressed in using ports as specified in the device graph bindings defined - in Documentation/devicetree/bindings/graph.txt. The numbering of the ports - is platform-specific. diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt deleted file mode 100644 index 3f6072651182..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +++ /dev/null @@ -1,88 +0,0 @@ -Renesas Gen3 DWC HDMI TX Encoder -================================ - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with a companion PHY IP. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - - -Required properties: - -- compatible : Shall contain one or more of - - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX - - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX - - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX - - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX - - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX - - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX - - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX - - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible - HDMI TX - - When compatible with generic versions, nodes must list the SoC-specific - version corresponding to the platform first, followed by the - family-specific version. - -- reg: See dw_hdmi.txt. -- interrupts: HDMI interrupt number -- clocks: See dw_hdmi.txt. -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. -- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0 - corresponding to the video input of the controller and one port numbered 1 - corresponding to its HDMI output, and one port numbered 2 corresponding to - sound input of the controller. Each port shall have a single endpoint. - -Optional properties: - -- power-domains: Shall reference the power domain that contains the DWC HDMI, - if any. - - -Example: - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - rcar_dw_hdmi0_sound_in: endpoint { - remote-endpoint = <&hdmi_sound_out>; - }; - }; - }; - }; - - hdmi0-out { - compatible = "hdmi-connector"; - label = "HDMI0 OUT"; - type = "a"; - - port { - hdmi0_con: endpoint { - remote-endpoint = <&rcar_dw_hdmi0_out>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml new file mode 100644 index 000000000000..0c9785c8db51 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car DWC HDMI TX Encoder + +maintainers: + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> + +description: | + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP + with a companion PHY IP. + +allOf: + - $ref: synopsys,dw-hdmi.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX + - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX + - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX + - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX + - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX + - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX + - renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX + - const: renesas,rcar-gen3-hdmi + + reg-io-width: + const: 1 + + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel RGB input port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Sound input port + + required: + - port@0 + - port@1 + - port@2 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7795-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/r8a7795-sysc.h> + + hdmi@fead0000 { + compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; + reg = <0xfead0000 0x10000>; + interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + port@2 { + reg = <2>; + rcar_dw_hdmi0_sound_in: endpoint { + remote-endpoint = <&hdmi_sound_out>; + }; + }; + }; + }; + + hdmi0-out { + compatible = "hdmi-connector"; + label = "HDMI0 OUT"; + type = "a"; + + port { + hdmi0_con: endpoint { + remote-endpoint = <&rcar_dw_hdmi0_out>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml new file mode 100644 index 000000000000..9be44a682e67 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Synopsys DesignWare HDMI TX Controller + +maintainers: + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> + +description: | + This document defines device tree properties for the Synopsys DesignWare HDMI + TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree + binding specification by itself but is meant to be referenced by device tree + bindings for the platform-specific integrations of the DWC HDMI TX. + + When referenced from platform device tree bindings the properties defined in + this document are defined as follows. The platform device tree bindings are + responsible for defining whether each property is required or optional. + +properties: + reg: + maxItems: 1 + + reg-io-width: + description: + Width (in bytes) of the registers specified by the reg property. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 4] + default: 1 + + clocks: + minItems: 2 + maxItems: 5 + items: + - description: The bus clock for either AHB and APB + - description: The internal register configuration clock + additionalItems: true + + clock-names: + minItems: 2 + maxItems: 5 + items: + - const: iahb + - const: isfr + additionalItems: true + + interrupts: + maxItems: 1 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml new file mode 100644 index 000000000000..af7fe9c4d196 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx6-hdmi.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 DWC HDMI TX Encoder + +maintainers: + - Philipp Zabel <p.zabel@pengutronix.de> + +description: | + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP + with a companion PHY IP. + +allOf: + - $ref: ../bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - fsl,imx6dl-hdmi + - fsl,imx6q-hdmi + + reg-io-width: + const: 1 + + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + ddc-i2c-bus: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The HDMI DDC bus can be connected to either a system I2C master or the + functionally-reduced I2C master contained in the DWC HDMI. When connected + to a system I2C master this property contains a phandle to that I2C + master controller. + + gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the iomuxc-gpr region containing the HDMI multiplexer control + register. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + This device has four video ports, corresponding to the four inputs of the + HDMI multiplexer. Each port shall have a single endpoint. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: First input of the HDMI multiplexer + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Second input of the HDMI multiplexer + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Third input of the HDMI multiplexer + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Fourth input of the HDMI multiplexer + + anyOf: + - required: + - port@0 + - required: + - port@1 + - required: + - port@2 + - required: + - port@3 + +required: + - compatible + - reg + - clocks + - clock-names + - gpr + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6qdl-clock.h> + + hdmi: hdmi@120000 { + reg = <0x00120000 0x9000>; + interrupts = <0 115 0x04>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HDMI_ISFR>; + clock-names = "iahb", "isfr"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_hdmi>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_hdmi>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/imx/hdmi.txt b/Documentation/devicetree/bindings/display/imx/hdmi.txt deleted file mode 100644 index 6d021e71c9cf..000000000000 --- a/Documentation/devicetree/bindings/display/imx/hdmi.txt +++ /dev/null @@ -1,65 +0,0 @@ -Freescale i.MX6 DWC HDMI TX Encoder -=================================== - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with a companion PHY IP. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - - -Required properties: - -- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi". -- reg: See dw_hdmi.txt. -- interrupts: HDMI interrupt number -- clocks: See dw_hdmi.txt. -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. -- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports, - numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer. - Each port shall have a single endpoint. -- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI - multiplexer control register. - -Optional properties - -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master - or the functionally-reduced I2C master contained in the DWC HDMI. When - connected to a system I2C master this property contains a phandle to that - I2C master controller. - - -Example: - - gpr: iomuxc-gpr@20e0000 { - /* ... */ - }; - - hdmi: hdmi@120000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-hdmi"; - reg = <0x00120000 0x9000>; - interrupts = <0 115 0x04>; - gpr = <&gpr>; - clocks = <&clks 123>, <&clks 124>; - clock-names = "iahb", "isfr"; - ddc-i2c-bus = <&i2c2>; - - port@0 { - reg = <0>; - - hdmi_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_hdmi>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_hdmi>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt deleted file mode 100644 index 7d65c24fcda8..000000000000 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ /dev/null @@ -1,145 +0,0 @@ -* Renesas R-Car Display Unit (DU) - -Required Properties: - - - compatible: must be one of the following. - - "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU - - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU - - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU - - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU - - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU - - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU - - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU - - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU - - "renesas,du-r8a774e1" for R8A774E1 (RZ/G2H) compatible DU - - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU - - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU - - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU - - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU - - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU - - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU - - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU - - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU - - "renesas,du-r8a77961" for R8A77961 (R-Car M3-W+) compatible DU - - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU - - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU - - "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU - - "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU - - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU - - - reg: the memory-mapped I/O registers base address and length - - - interrupts: Interrupt specifiers for the DU interrupts. - - - clocks: A list of phandles + clock-specifier pairs, one for each entry in - the clock-names property. - - clock-names: Name of the clocks. This property is model-dependent. - - R8A7779 uses a single functional clock. The clock doesn't need to be - named. - - All other DU instances use one functional clock per channel The - functional clocks must be named "du.x" with "x" being the channel - numerical index. - - In addition to the functional clocks, all DU versions also support - externally supplied pixel clocks. Those clocks are optional. When - supplied they must be named "dclkin.x" with "x" being the input clock - numerical index. - - - renesas,cmms: A list of phandles to the CMM instances present in the SoC, - one for each available DU channel. The property shall not be specified for - SoCs that do not provide any CMM (such as V3M and V3H). - - - renesas,vsps: A list of phandle and channel index tuples to the VSPs that - handle the memory interfaces for the DU channels. The phandle identifies the - VSP instance that serves the DU channel, and the channel index identifies - the LIF instance in that VSP. - -Optional properties: - - resets: A list of phandle + reset-specifier pairs, one for each entry in - the reset-names property. - - reset-names: Names of the resets. This property is model-dependent. - - All but R8A7779 use one reset for a group of one or more successive - channels. The resets must be named "du.x" with "x" being the numerical - index of the lowest channel in the group. - -Required nodes: - -The connections to the DU output video ports are modeled using the OF graph -bindings specified in Documentation/devicetree/bindings/graph.txt. - -The following table lists for each supported model the port number -corresponding to each DU output. - - Port0 Port1 Port2 Port3 ------------------------------------------------------------------------------ - R8A7742 (RZ/G1H) DPAD 0 LVDS 0 LVDS 1 - - R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - - - R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - - - R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - - R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 - - R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 - - R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 - - R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 - - R8A774E1 (RZ/G2H) DPAD 0 HDMI 0 LVDS 0 - - R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - - R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - - R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - - - R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - - - R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - - - R8A7794 (R-Car E2) DPAD 0 DPAD 1 - - - R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0 - R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 - - R8A77961 (R-Car M3-W+) DPAD 0 HDMI 0 LVDS 0 - - R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 - - R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - - - R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - - - R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 - - R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 - - - -Example: R8A7795 (R-Car H3) ES2.0 DU - - du: display@feb00000 { - compatible = "renesas,du-r8a7795"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.2", "du.3"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.2"; - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_hdmi1: endpoint { - remote-endpoint = <&dw_hdmi1_in>; - }; - }; - port@3 { - reg = <3>; - du_out_lvds0: endpoint { - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml new file mode 100644 index 000000000000..552a99ce4f12 --- /dev/null +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml @@ -0,0 +1,831 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/renesas,du.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Display Unit (DU) + +maintainers: + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> + +description: | + These DT bindings describe the Display Unit embedded in the Renesas R-Car + Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs. + +properties: + compatible: + enum: + - renesas,du-r8a7742 # for RZ/G1H compatible DU + - renesas,du-r8a7743 # for RZ/G1M compatible DU + - renesas,du-r8a7744 # for RZ/G1N compatible DU + - renesas,du-r8a7745 # for RZ/G1E compatible DU + - renesas,du-r8a77470 # for RZ/G1C compatible DU + - renesas,du-r8a774a1 # for RZ/G2M compatible DU + - renesas,du-r8a774b1 # for RZ/G2N compatible DU + - renesas,du-r8a774c0 # for RZ/G2E compatible DU + - renesas,du-r8a774e1 # for RZ/G2H compatible DU + - renesas,du-r8a7779 # for R-Car H1 compatible DU + - renesas,du-r8a7790 # for R-Car H2 compatible DU + - renesas,du-r8a7791 # for R-Car M2-W compatible DU + - renesas,du-r8a7792 # for R-Car V2H compatible DU + - renesas,du-r8a7793 # for R-Car M2-N compatible DU + - renesas,du-r8a7794 # for R-Car E2 compatible DU + - renesas,du-r8a7795 # for R-Car H3 compatible DU + - renesas,du-r8a7796 # for R-Car M3-W compatible DU + - renesas,du-r8a77961 # for R-Car M3-W+ compatible DU + - renesas,du-r8a77965 # for R-Car M3-N compatible DU + - renesas,du-r8a77970 # for R-Car V3M compatible DU + - renesas,du-r8a77980 # for R-Car V3H compatible DU + - renesas,du-r8a77990 # for R-Car E3 compatible DU + - renesas,du-r8a77995 # for R-Car D3 compatible DU + + reg: + maxItems: 1 + + # See compatible-specific constraints below. + clocks: true + clock-names: true + interrupts: + description: Interrupt specifiers, one per DU channel + resets: true + reset-names: true + + ports: + $ref: /schemas/graph.yaml#/properties/port + description: | + The connections to the DU output video ports are modeled using the OF + graph bindings specified in Documentation/devicetree/bindings/graph.txt. + The number of ports and their assignment are model-dependent. Each port + shall have a single endpoint. + + patternProperties: + "^port@[0-3]$": + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + + required: + - port@0 + - port@1 + + unevaluatedProperties: false + + renesas,cmms: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + A list of phandles to the CMM instances present in the SoC, one for each + available DU channel. + + renesas,vsps: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + A list of phandle and channel index tuples to the VSPs that handle the + memory interfaces for the DU channels. The phandle identifies the VSP + instance that serves the DU channel, and the channel index identifies + the LIF instance in that VSP. + +required: + - compatible + - reg + - clocks + - interrupts + - resets + - ports + +allOf: + - if: + properties: + compatible: + contains: + const: renesas,du-r8a7779 + then: + properties: + clocks: + minItems: 1 + maxItems: 3 + items: + - description: Functional clock + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 1 + maxItems: 3 + items: + - const: du.0 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: DPAD 1 + # port@2 is TCON, not supported yet + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + required: + - interrupts + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a7743 + - renesas,du-r8a7744 + - renesas,du-r8a7791 + - renesas,du-r8a7793 + then: + properties: + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: du.0 + - const: du.1 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: LVDS 0 + # port@2 is TCON, not supported yet + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + required: + - clock-names + - interrupts + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a7745 + - renesas,du-r8a7792 + then: + properties: + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: du.0 + - const: du.1 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: DPAD 1 + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + required: + - clock-names + - interrupts + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a7794 + then: + properties: + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: du.0 + - const: du.1 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: DPAD 1 + # port@2 is TCON, not supported yet + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + required: + - clock-names + - interrupts + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a77470 + then: + properties: + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: du.0 + - const: du.1 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: DPAD 1 + port@2: + description: LVDS 0 + # port@3 is DVENC, not supported yet + port@3: false + + required: + - port@0 + - port@1 + - port@2 + + required: + - clock-names + - interrupts + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a7742 + - renesas,du-r8a7790 + then: + properties: + clocks: + minItems: 3 + maxItems: 6 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: Functional clock for DU2 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + - description: DU_DOTCLKIN2 input clock + + clock-names: + minItems: 3 + maxItems: 6 + items: + - const: du.0 + - const: du.1 + - const: du.2 + - pattern: '^dclkin\.[012]$' + - pattern: '^dclkin\.[012]$' + - pattern: '^dclkin\.[012]$' + + interrupts: + maxItems: 3 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: LVDS 0 + port@2: + description: LVDS 1 + # port@3 is TCON, not supported yet + port@3: false + + required: + - port@0 + - port@1 + - port@2 + + required: + - clock-names + - interrupts + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a7795 + then: + properties: + clocks: + minItems: 4 + maxItems: 8 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: Functional clock for DU2 + - description: Functional clock for DU4 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + - description: DU_DOTCLKIN2 input clock + - description: DU_DOTCLKIN3 input clock + + clock-names: + minItems: 4 + maxItems: 8 + items: + - const: du.0 + - const: du.1 + - const: du.2 + - const: du.3 + - pattern: '^dclkin\.[0123]$' + - pattern: '^dclkin\.[0123]$' + - pattern: '^dclkin\.[0123]$' + - pattern: '^dclkin\.[0123]$' + + interrupts: + maxItems: 4 + + resets: + maxItems: 2 + + reset-names: + items: + - const: du.0 + - const: du.2 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: HDMI 0 + port@2: + description: HDMI 1 + port@3: + description: LVDS 0 + + required: + - port@0 + - port@1 + - port@2 + - port@3 + + renesas,cmms: + minItems: 4 + + renesas,vsps: + minItems: 4 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a774a1 + - renesas,du-r8a7796 + - renesas,du-r8a77961 + then: + properties: + clocks: + minItems: 3 + maxItems: 6 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: Functional clock for DU2 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + - description: DU_DOTCLKIN2 input clock + + clock-names: + minItems: 3 + maxItems: 6 + items: + - const: du.0 + - const: du.1 + - const: du.2 + - pattern: '^dclkin\.[012]$' + - pattern: '^dclkin\.[012]$' + - pattern: '^dclkin\.[012]$' + + interrupts: + maxItems: 3 + + resets: + maxItems: 2 + + reset-names: + items: + - const: du.0 + - const: du.2 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: HDMI 0 + port@2: + description: LVDS 0 + port@3: false + + required: + - port@0 + - port@1 + - port@2 + + renesas,cmms: + minItems: 3 + + renesas,vsps: + minItems: 3 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a774b1 + - renesas,du-r8a774e1 + - renesas,du-r8a77965 + then: + properties: + clocks: + minItems: 3 + maxItems: 6 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: Functional clock for DU3 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + - description: DU_DOTCLKIN3 input clock + + clock-names: + minItems: 3 + maxItems: 6 + items: + - const: du.0 + - const: du.1 + - const: du.3 + - pattern: '^dclkin\.[013]$' + - pattern: '^dclkin\.[013]$' + - pattern: '^dclkin\.[013]$' + + interrupts: + maxItems: 3 + + resets: + maxItems: 2 + + reset-names: + items: + - const: du.0 + - const: du.3 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: HDMI 0 + port@2: + description: LVDS 0 + port@3: false + + required: + - port@0 + - port@1 + - port@2 + + renesas,cmms: + minItems: 3 + + renesas,vsps: + minItems: 3 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a77970 + - renesas,du-r8a77980 + then: + properties: + clocks: + minItems: 1 + maxItems: 2 + items: + - description: Functional clock for DU0 + - description: DU_DOTCLKIN0 input clock + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: du.0 + - const: dclkin.0 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: LVDS 0 + port@2: false + port@3: false + + required: + - port@0 + - port@1 + + renesas,vsps: + minItems: 1 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + + - if: + properties: + compatible: + contains: + enum: + - renesas,du-r8a774c0 + - renesas,du-r8a77990 + - renesas,du-r8a77995 + then: + properties: + clocks: + minItems: 2 + maxItems: 4 + items: + - description: Functional clock for DU0 + - description: Functional clock for DU1 + - description: DU_DOTCLKIN0 input clock + - description: DU_DOTCLKIN1 input clock + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: du.0 + - const: du.1 + - pattern: '^dclkin\.[01]$' + - pattern: '^dclkin\.[01]$' + + interrupts: + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + items: + - const: du.0 + + ports: + properties: + port@0: + description: DPAD 0 + port@1: + description: LVDS 0 + port@2: + description: LVDS 1 + # port@3 is TCON, not supported yet + port@3: false + + required: + - port@0 + - port@1 + - port@2 + + renesas,cmms: + minItems: 2 + + renesas,vsps: + minItems: 2 + + required: + - clock-names + - interrupts + - resets + - reset-names + - renesas,vsps + +additionalProperties: false + +examples: + # R-Car H3 ES2.0 DU + - | + #include <dt-bindings/clock/renesas-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + display@feb00000 { + compatible = "renesas,du-r8a7795"; + reg = <0xfeb00000 0x80000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.2", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.2"; + + renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dw_hdmi0_in>; + }; + }; + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&dw_hdmi1_in>; + }; + }; + port@3 { + reg = <3>; + endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt deleted file mode 100644 index 3d32ce137e7f..000000000000 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ /dev/null @@ -1,74 +0,0 @@ -Rockchip DWC HDMI TX Encoder -============================ - -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP -with a companion PHY IP. - -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the -following device-specific properties. - - -Required properties: - -- compatible: should be one of the following: - "rockchip,rk3228-dw-hdmi" - "rockchip,rk3288-dw-hdmi" - "rockchip,rk3328-dw-hdmi" - "rockchip,rk3399-dw-hdmi" -- reg: See dw_hdmi.txt. -- reg-io-width: See dw_hdmi.txt. Shall be 4. -- interrupts: HDMI interrupt number -- clocks: See dw_hdmi.txt. -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0 - corresponding to the video input of the controller. The port shall have two - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl. -- rockchip,grf: Shall reference the GRF to mux vopl/vopb. - -Optional properties - -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master - or the functionally-reduced I2C master contained in the DWC HDMI. When - connected to a system I2C master this property contains a phandle to that - I2C master controller. -- clock-names: See dw_hdmi.txt. The "cec" clock is optional. -- clock-names: May contain "cec" as defined in dw_hdmi.txt. -- clock-names: May contain "grf", power for grf io. -- clock-names: May contain "vpll", external clock for some hdmi phy. -- phys: from general PHY binding: the phandle for the PHY device. -- phy-names: Should be "hdmi" if phys references an external phy. - -Optional pinctrl entry: -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi - will switch to the unwedge pinctrl state for 10ms if it ever gets an - i2c timeout. It's intended that this unwedge pinctrl entry will - cause the SDA line to be driven low to work around a hardware - errata. - -Example: - -hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0xff980000 0x20000>; - reg-io-width = <4>; - ddc-i2c-bus = <&i2c5>; - rockchip,grf = <&grf>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; - clock-names = "iahb", "isfr"; - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - hdmi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml new file mode 100644 index 000000000000..75cd9c686e98 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip DWC HDMI TX Encoder + +maintainers: + - Mark Yao <markyao0591@gmail.com> + +description: | + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP + with a companion PHY IP. + +allOf: + - $ref: ../bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - rockchip,rk3228-dw-hdmi + - rockchip,rk3288-dw-hdmi + - rockchip,rk3328-dw-hdmi + - rockchip,rk3399-dw-hdmi + + reg-io-width: + const: 4 + + clocks: + minItems: 2 + maxItems: 5 + items: + - {} + - {} + # The next three clocks are all optional, but shall be specified in this + # order when present. + - description: The HDMI CEC controller main clock + - description: Power for GRF IO + - description: External clock for some HDMI PHY + + clock-names: + minItems: 2 + maxItems: 5 + items: + - {} + - {} + - enum: + - cec + - grf + - vpll + - enum: + - grf + - vpll + - const: vpll + + ddc-i2c-bus: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The HDMI DDC bus can be connected to either a system I2C master or the + functionally-reduced I2C master contained in the DWC HDMI. When connected + to a system I2C master this property contains a phandle to that I2C + master controller. + + phys: + maxItems: 1 + description: The HDMI PHY + + phy-names: + const: hdmi + + pinctrl-names: + description: + The unwedge pinctrl entry shall drive the DDC SDA line low. This is + intended to work around a hardware errata that can cause the DDC I2C + bus to be wedged. + items: + - const: default + - const: unwedge + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Input of the DWC HDMI TX + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: Connection to the VOPB + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + description: Connection to the VOPL + + required: + - endpoint@0 + - endpoint@1 + + required: + - port + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the GRF to mux vopl/vopb. + +required: + - compatible + - reg + - reg-io-width + - clocks + - clock-names + - interrupts + - ports + - rockchip,grf + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3288-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + hdmi: hdmi@ff980000 { + compatible = "rockchip,rk3288-dw-hdmi"; + reg = <0xff980000 0x20000>; + reg-io-width = <4>; + ddc-i2c-bus = <&i2c5>; + rockchip,grf = <&grf>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; + clock-names = "iahb", "isfr"; + + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index fbae9a19d017..fa231a491463 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5988,9 +5988,9 @@ L: dri-devel@lists.freedesktop.org L: linux-renesas-soc@vger.kernel.org S: Supported T: git git://linuxtv.org/pinchartl/media drm/du/next -F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml -F: Documentation/devicetree/bindings/display/renesas,du.txt +F: Documentation/devicetree/bindings/display/renesas,du.yaml F: drivers/gpu/drm/rcar-du/ F: drivers/gpu/drm/shmobile/ F: include/linux/platform_data/shmob_drm.h |