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-rw-r--r--arch/ppc/platforms/4xx/Kconfig285
-rw-r--r--arch/ppc/platforms/4xx/Makefile31
-rw-r--r--arch/ppc/platforms/4xx/bamboo.c442
-rw-r--r--arch/ppc/platforms/4xx/bamboo.h133
-rw-r--r--arch/ppc/platforms/4xx/bubinga.c265
-rw-r--r--arch/ppc/platforms/4xx/bubinga.h54
-rw-r--r--arch/ppc/platforms/4xx/cpci405.c201
-rw-r--r--arch/ppc/platforms/4xx/cpci405.h28
-rw-r--r--arch/ppc/platforms/4xx/ebony.c334
-rw-r--r--arch/ppc/platforms/4xx/ebony.h97
-rw-r--r--arch/ppc/platforms/4xx/ep405.c196
-rw-r--r--arch/ppc/platforms/4xx/ep405.h52
-rw-r--r--arch/ppc/platforms/4xx/ibm405ep.c141
-rw-r--r--arch/ppc/platforms/4xx/ibm405ep.h145
-rw-r--r--arch/ppc/platforms/4xx/ibm405gp.c120
-rw-r--r--arch/ppc/platforms/4xx/ibm405gp.h148
-rw-r--r--arch/ppc/platforms/4xx/ibm405gpr.c115
-rw-r--r--arch/ppc/platforms/4xx/ibm405gpr.h148
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.c220
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.h73
-rw-r--r--arch/ppc/platforms/4xx/ibm440gp.c163
-rw-r--r--arch/ppc/platforms/4xx/ibm440gp.h63
-rw-r--r--arch/ppc/platforms/4xx/ibm440gx.c231
-rw-r--r--arch/ppc/platforms/4xx/ibm440gx.h71
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.c129
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.h61
-rw-r--r--arch/ppc/platforms/4xx/ibmnp405h.c170
-rw-r--r--arch/ppc/platforms/4xx/ibmnp405h.h154
-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.c122
-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.h235
-rw-r--r--arch/ppc/platforms/4xx/ibmstbx25.c66
-rw-r--r--arch/ppc/platforms/4xx/ibmstbx25.h258
-rw-r--r--arch/ppc/platforms/4xx/luan.c371
-rw-r--r--arch/ppc/platforms/4xx/luan.h77
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c350
-rw-r--r--arch/ppc/platforms/4xx/ocotea.h94
-rw-r--r--arch/ppc/platforms/4xx/ppc440spe.c146
-rw-r--r--arch/ppc/platforms/4xx/ppc440spe.h63
-rw-r--r--arch/ppc/platforms/4xx/redwood5.c120
-rw-r--r--arch/ppc/platforms/4xx/redwood5.h52
-rw-r--r--arch/ppc/platforms/4xx/redwood6.c156
-rw-r--r--arch/ppc/platforms/4xx/redwood6.h53
-rw-r--r--arch/ppc/platforms/4xx/sycamore.c272
-rw-r--r--arch/ppc/platforms/4xx/sycamore.h49
-rw-r--r--arch/ppc/platforms/4xx/taishan.c395
-rw-r--r--arch/ppc/platforms/4xx/taishan.h67
-rw-r--r--arch/ppc/platforms/4xx/virtex.h35
-rw-r--r--arch/ppc/platforms/4xx/walnut.c246
-rw-r--r--arch/ppc/platforms/4xx/walnut.h52
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml300.c118
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml403.c120
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters.h104
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h310
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h243
-rw-r--r--arch/ppc/platforms/4xx/yucca.c393
-rw-r--r--arch/ppc/platforms/4xx/yucca.h108
56 files changed, 0 insertions, 8945 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
deleted file mode 100644
index 76551b679030..000000000000
--- a/arch/ppc/platforms/4xx/Kconfig
+++ /dev/null
@@ -1,285 +0,0 @@
-config 4xx
- bool
- depends on 40x || 44x
- default y
-
-config WANT_EARLY_SERIAL
- bool
- select SERIAL_8250
- default n
-
-menu "IBM 4xx options"
- depends on 4xx
-
-choice
- prompt "Machine Type"
- depends on 40x
- default WALNUT
-
-config BUBINGA
- bool "Bubinga"
- select WANT_EARLY_SERIAL
- help
- This option enables support for the IBM 405EP evaluation board.
-
-config CPCI405
- bool "CPCI405"
- help
- This option enables support for the CPCI405 board.
-
-config EP405
- bool "EP405/EP405PC"
- select EMBEDDEDBOOT
- help
- This option enables support for the EP405/EP405PC boards.
-
-config REDWOOD_5
- bool "Redwood-5"
- help
- This option enables support for the IBM STB04 evaluation board.
-
-config REDWOOD_6
- bool "Redwood-6"
- help
- This option enables support for the IBM STBx25xx evaluation board.
-
-config SYCAMORE
- bool "Sycamore"
- help
- This option enables support for the IBM PPC405GPr evaluation board.
-
-config WALNUT
- bool "Walnut"
- help
- This option enables support for the IBM PPC405GP evaluation board.
-
-config XILINX_ML300
- bool "Xilinx-ML300"
- select XILINX_VIRTEX_II_PRO
- select EMBEDDEDBOOT
- help
- This option enables support for the Xilinx ML300 evaluation board.
-
-config XILINX_ML403
- bool "Xilinx-ML403"
- select XILINX_VIRTEX_4_FX
- select EMBEDDEDBOOT
- help
- This option enables support for the Xilinx ML403 evaluation board.
-endchoice
-
-choice
- prompt "Machine Type"
- depends on 44x
- default EBONY
-
-config BAMBOO
- bool "Bamboo"
- select WANT_EARLY_SERIAL
- help
- This option enables support for the IBM PPC440EP evaluation board.
-
-config EBONY
- bool "Ebony"
- select WANT_EARLY_SERIAL
- help
- This option enables support for the IBM PPC440GP evaluation board.
-
-config LUAN
- bool "Luan"
- select WANT_EARLY_SERIAL
- help
- This option enables support for the IBM PPC440SP evaluation board.
-
-config YUCCA
- bool "Yucca"
- select WANT_EARLY_SERIAL
- help
- This option enables support for the AMCC PPC440SPe evaluation board.
-
-config OCOTEA
- bool "Ocotea"
- select WANT_EARLY_SERIAL
- help
- This option enables support for the IBM PPC440GX evaluation board.
-
-config TAISHAN
- bool "Taishan"
- select WANT_EARLY_SERIAL
- help
- This option enables support for the AMCC PPC440GX evaluation board.
-
-endchoice
-
-config EP405PC
- bool "EP405PC Support"
- depends on EP405
-
-
-# It's often necessary to know the specific 4xx processor type.
-# Fortunately, it is impled (so far) from the board type, so we
-# don't need to ask more redundant questions.
-config NP405H
- bool
- depends on ASH
- default y
-
-config 440EP
- bool
- depends on BAMBOO
- select PPC_FPU
- default y
-
-config 440GP
- bool
- depends on EBONY
- default y
-
-config 440GX
- bool
- depends on OCOTEA || TAISHAN
- default y
-
-config 440SP
- bool
- depends on LUAN
- default y
-
-config 440SPE
- bool
- depends on YUCCA
- default y
-
-config 440
- bool
- depends on 440GP || 440SP || 440SPE || 440EP
- default y
-
-config 440A
- bool
- depends on 440GX
- default y
-
-config IBM440EP_ERR42
- bool
- depends on 440EP
- default y
-
-# All 405-based cores up until the 405GPR and 405EP have this errata.
-config IBM405_ERR77
- bool
- depends on 40x && !403GCX && !405GPR && !405EP
- default y
-
-# All 40x-based cores, up until the 405GPR and 405EP have this errata.
-config IBM405_ERR51
- bool
- depends on 40x && !405GPR && !405EP
- default y
-
-config BOOKE
- bool
- depends on 44x
- default y
-
-config IBM_OCP
- bool
- depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT
- default y
-
-config IBM_EMAC4
- bool
- depends on 440GX || 440SP || 440SPE
- default y
-
-config BIOS_FIXUP
- bool
- depends on BUBINGA || EP405 || SYCAMORE || WALNUT || CPCI405
- default y
-
-# OAK doesn't exist but wanted to keep this around for any future 403GCX boards
-config 403GCX
- bool
- depends on OAK
- default y
-
-config 405EP
- bool
- depends on BUBINGA
- default y
-
-config 405GP
- bool
- depends on CPCI405 || EP405 || WALNUT
- default y
-
-config 405GPR
- bool
- depends on SYCAMORE
- default y
-
-config XILINX_VIRTEX_II_PRO
- bool
- select XILINX_VIRTEX
-
-config XILINX_VIRTEX_4_FX
- bool
- select XILINX_VIRTEX
-
-config XILINX_VIRTEX
- bool
-
-config STB03xxx
- bool
- depends on REDWOOD_5 || REDWOOD_6
- default y
-
-config EMBEDDEDBOOT
- bool
-
-config IBM_OPENBIOS
- bool
- depends on ASH || REDWOOD_5 || REDWOOD_6
- default y
-
-config PPC4xx_DMA
- bool "PPC4xx DMA controller support"
- depends on 4xx
-
-config PPC4xx_EDMA
- bool
- depends on !STB03xxx && PPC4xx_DMA
- default y
-
-config PPC_GEN550
- bool
- depends on 4xx
- default y
-
-choice
- prompt "TTYS0 device and default console"
- depends on 40x
- default UART0_TTYS0
-
-config UART0_TTYS0
- bool "UART0"
-
-config UART0_TTYS1
- bool "UART1"
-
-endchoice
-
-config SERIAL_SICC
- bool "SICC Serial port support"
- depends on STB03xxx
-
-config UART1_DFLT_CONSOLE
- bool
- depends on SERIAL_SICC && UART0_TTYS1
- default y
-
-config SERIAL_SICC_CONSOLE
- bool
- depends on SERIAL_SICC && UART0_TTYS1
- default y
-endmenu
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
deleted file mode 100644
index 723ad7985cc6..000000000000
--- a/arch/ppc/platforms/4xx/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# Makefile for the PowerPC 4xx linux kernel.
-
-obj-$(CONFIG_BAMBOO) += bamboo.o
-obj-$(CONFIG_CPCI405) += cpci405.o
-obj-$(CONFIG_EBONY) += ebony.o
-obj-$(CONFIG_EP405) += ep405.o
-obj-$(CONFIG_BUBINGA) += bubinga.o
-obj-$(CONFIG_LUAN) += luan.o
-obj-$(CONFIG_YUCCA) += yucca.o
-obj-$(CONFIG_OCOTEA) += ocotea.o
-obj-$(CONFIG_REDWOOD_5) += redwood5.o
-obj-$(CONFIG_REDWOOD_6) += redwood6.o
-obj-$(CONFIG_SYCAMORE) += sycamore.o
-obj-$(CONFIG_TAISHAN) += taishan.o
-obj-$(CONFIG_WALNUT) += walnut.o
-obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o
-obj-$(CONFIG_XILINX_ML403) += xilinx_ml403.o
-
-obj-$(CONFIG_405GP) += ibm405gp.o
-obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
-obj-$(CONFIG_NP405H) += ibmnp405h.o
-obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
-obj-$(CONFIG_440EP) += ibm440ep.o
-obj-$(CONFIG_440GP) += ibm440gp.o
-obj-$(CONFIG_440GX) += ibm440gx.o
-obj-$(CONFIG_440SP) += ibm440sp.o
-obj-$(CONFIG_440SPE) += ppc440spe.o
-obj-$(CONFIG_405EP) += ibm405ep.o
-obj-$(CONFIG_405GPR) += ibm405gpr.o
-
diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c
deleted file mode 100644
index 01f20f4c14fe..000000000000
--- a/arch/ppc/platforms/4xx/bamboo.c
+++ /dev/null
@@ -1,442 +0,0 @@
-/*
- * Bamboo board specific routines
- *
- * Wade Farnsworth <wfarnsworth@mvista.com>
- * Copyright 2004 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/ethtool.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/pci-bridge.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/ppcboot.h>
-
-#include <syslib/gen550.h>
-#include <syslib/ibm440gx_common.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-/*
- * Bamboo external IRQ triggering/polarity settings
- */
-unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
-};
-
-static void __init
-bamboo_calibrate_decr(void)
-{
- unsigned int freq;
-
- if (mfspr(SPRN_CCR1) & CCR1_TCS)
- freq = BAMBOO_TMRCLK;
- else
- freq = clocks.cpu;
-
- ibm44x_calibrate_decr(freq);
-
-}
-
-static int
-bamboo_show_cpuinfo(struct seq_file *m)
-{
- seq_printf(m, "vendor\t\t: IBM\n");
- seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
-
- return 0;
-}
-
-static inline int
-bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 28, 28, 28, 28 }, /* IDSEL 1 - PCI Slot 0 */
- { 27, 27, 27, 27 }, /* IDSEL 2 - PCI Slot 1 */
- { 26, 26, 26, 26 }, /* IDSEL 3 - PCI Slot 2 */
- { 25, 25, 25, 25 }, /* IDSEL 4 - PCI Slot 3 */
- };
-
- const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static void __init bamboo_set_emacdata(void)
-{
- u8 * base_addr;
- struct ocp_def *def;
- struct ocp_func_emac_data *emacdata;
- u8 val;
- int mode;
- u32 excluded = 0;
-
- base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
- val = readb(base_addr);
- iounmap((void *) base_addr);
- if (BAMBOO_SEL_MII(val))
- mode = PHY_MODE_MII;
- else if (BAMBOO_SEL_RMII(val))
- mode = PHY_MODE_RMII;
- else
- mode = PHY_MODE_SMII;
-
- /*
- * SW2 on the Bamboo is used for ethernet configuration and is accessed
- * via the CONFIG2 register in the FPGA. If the ANEG pin is set,
- * overwrite the supported features with the settings in SW2.
- *
- * This is used as a workaround for the improperly biased RJ-45 sockets
- * on the Rev. 0 Bamboo. By default only 10baseT is functional.
- * Removing inductors L17 and L18 from the board allows 100baseT, but
- * disables 10baseT. The Rev. 1 has no such limitations.
- */
-
- base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
- val = readb(base_addr);
- iounmap((void *) base_addr);
- if (!BAMBOO_AUTONEGOTIATE(val)) {
- excluded |= SUPPORTED_Autoneg;
- if (BAMBOO_FORCE_100Mbps(val)) {
- excluded |= SUPPORTED_10baseT_Full;
- excluded |= SUPPORTED_10baseT_Half;
- if (BAMBOO_FULL_DUPLEX_EN(val))
- excluded |= SUPPORTED_100baseT_Half;
- else
- excluded |= SUPPORTED_100baseT_Full;
- } else {
- excluded |= SUPPORTED_100baseT_Full;
- excluded |= SUPPORTED_100baseT_Half;
- if (BAMBOO_FULL_DUPLEX_EN(val))
- excluded |= SUPPORTED_10baseT_Half;
- else
- excluded |= SUPPORTED_10baseT_Full;
- }
- }
-
- /* Set mac_addr, phy mode and unsupported phy features for each EMAC */
-
- def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
- emacdata = def->additions;
- memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
- emacdata->phy_mode = mode;
- emacdata->phy_feat_exc = excluded;
-
- def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
- emacdata = def->additions;
- memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
- emacdata->phy_mode = mode;
- emacdata->phy_feat_exc = excluded;
-}
-
-static int
-bamboo_exclude_device(unsigned char bus, unsigned char devfn)
-{
- return (bus == 0 && devfn == 0);
-}
-
-#define PCI_READW(offset) \
- (readw((void *)((u32)pci_reg_base+offset)))
-
-#define PCI_WRITEW(value, offset) \
- (writew(value, (void *)((u32)pci_reg_base+offset)))
-
-#define PCI_WRITEL(value, offset) \
- (writel(value, (void *)((u32)pci_reg_base+offset)))
-
-static void __init
-bamboo_setup_pci(void)
-{
- void *pci_reg_base;
- unsigned long memory_size;
- memory_size = ppc_md.find_end_of_memory();
-
- pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
-
- /* Enable PCI I/O, Mem, and Busmaster cycles */
- PCI_WRITEW(PCI_READW(PCI_COMMAND) |
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER, PCI_COMMAND);
-
- /* Disable region first */
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
-
- /* PLB starting addr: 0x00000000A0000000 */
- PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
-
- /* PCI start addr, 0xA0000000 (PCI Address) */
- PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
-
- /* Enable no pre-fetch, enable region */
- PCI_WRITEL(((0xffffffff -
- (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
- BAMBOO_PCIL0_PMM0MA);
-
- /* Disable region one */
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
-
- /* Disable region two */
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
- PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
-
- /* Now configure the PCI->PLB windows, we only use PTM1
- *
- * For Inbound flow, set the window size to all available memory
- * This is required because if size is smaller,
- * then Eth/PCI DD would fail as PCI card not able to access
- * the memory allocated by DD.
- */
-
- PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */
- PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */
-
- memory_size = 1 << fls(memory_size - 1);
-
- /* Size low + Enabled */
- PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
-
- eieio();
- iounmap(pci_reg_base);
-}
-
-static void __init
-bamboo_setup_hose(void)
-{
- unsigned int bar_response, bar;
- struct pci_controller *hose;
-
- bamboo_setup_pci();
-
- hose = pcibios_alloc_controller();
-
- if (!hose)
- return;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
-
- pci_init_resource(&hose->io_resource,
- BAMBOO_PCI_LOWER_IO,
- BAMBOO_PCI_UPPER_IO,
- IORESOURCE_IO,
- "PCI host bridge");
-
- pci_init_resource(&hose->mem_resources[0],
- BAMBOO_PCI_LOWER_MEM,
- BAMBOO_PCI_UPPER_MEM,
- IORESOURCE_MEM,
- "PCI host bridge");
-
- ppc_md.pci_exclude_device = bamboo_exclude_device;
-
- hose->io_space.start = BAMBOO_PCI_LOWER_IO;
- hose->io_space.end = BAMBOO_PCI_UPPER_IO;
- hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
- hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
- isa_io_base =
- (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
- hose->io_base_virt = (void *)isa_io_base;
-
- setup_indirect_pci(hose,
- BAMBOO_PCI_CFGA_PLB32,
- BAMBOO_PCI_CFGD_PLB32);
- hose->set_cfg_type = 1;
-
- /* Zero config bars */
- for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
- early_write_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- 0x00000000);
- early_read_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- &bar_response);
- }
-
- hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
- ppc_md.pci_swizzle = common_swizzle;
- ppc_md.pci_map_irq = bamboo_map_irq;
-}
-
-TODC_ALLOC();
-
-static void __init
-bamboo_early_serial_map(void)
-{
- struct uart_port port;
-
- /* Setup ioremapped serial port access */
- memset(&port, 0, sizeof(port));
- port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
- port.irq = 0;
- port.uartclk = clocks.uart0;
- port.regshift = 0;
- port.iotype = UPIO_MEM;
- port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- port.line = 0;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 0 failed\n");
- }
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- /* Configure debug serial access */
- gen550_init(0, &port);
-#endif
-
- port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
- port.irq = 1;
- port.uartclk = clocks.uart1;
- port.line = 1;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 1 failed\n");
- }
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- /* Configure debug serial access */
- gen550_init(1, &port);
-#endif
-
- port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
- port.irq = 3;
- port.uartclk = clocks.uart2;
- port.line = 2;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 2 failed\n");
- }
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- /* Configure debug serial access */
- gen550_init(2, &port);
-#endif
-
- port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
- port.irq = 4;
- port.uartclk = clocks.uart3;
- port.line = 3;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 3 failed\n");
- }
-}
-
-static void __init
-bamboo_setup_arch(void)
-{
-
- bamboo_set_emacdata();
-
- ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
- ocp_sys_info.opb_bus_freq = clocks.opb;
-
- /* Setup TODC access */
- TODC_INIT(TODC_TYPE_DS1743,
- 0,
- 0,
- ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
- 8);
-
- /* init to some ~sane value until calibrate_delay() runs */
- loops_per_jiffy = 50000000/HZ;
-
- /* Setup PCI host bridge */
- bamboo_setup_hose();
-
-#ifdef CONFIG_BLK_DEV_INITRD
- if (initrd_start)
- ROOT_DEV = Root_RAM0;
- else
-#endif
-#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
-#else
- ROOT_DEV = Root_HDA1;
-#endif
-
- bamboo_early_serial_map();
-
- /* Identify the system */
- printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
- unsigned long r5, unsigned long r6, unsigned long r7)
-{
- ibm44x_platform_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = bamboo_setup_arch;
- ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
- ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
-
- ppc_md.calibrate_decr = bamboo_calibrate_decr;
- ppc_md.time_init = todc_time_init;
- ppc_md.set_rtc_time = todc_set_rtc_time;
- ppc_md.get_rtc_time = todc_get_rtc_time;
-
- ppc_md.nvram_read_val = todc_direct_read_val;
- ppc_md.nvram_write_val = todc_direct_write_val;
-#ifdef CONFIG_KGDB
- ppc_md.early_serial_map = bamboo_early_serial_map;
-#endif
-}
-
diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h
deleted file mode 100644
index dcd3d09a0a71..000000000000
--- a/arch/ppc/platforms/4xx/bamboo.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Bamboo board definitions
- *
- * Wade Farnsworth <wfarnsworth@mvista.com>
- *
- * Copyright 2004 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_BAMBOO_H__
-#define __ASM_BAMBOO_H__
-
-#include <platforms/4xx/ibm440ep.h>
-
-/* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0 0x0EF600E00
-
-/* Location of MAC addresses in PIBS image */
-#define PIBS_FLASH_BASE 0xfff00000
-#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xc0400)
-#define PIBS_MAC_SIZE 0x200
-#define PIBS_MAC_OFFSET 0x100
-
-/* Default clock rate */
-#define BAMBOO_TMRCLK 25000000
-
-/* RTC/NVRAM location */
-#define BAMBOO_RTC_ADDR 0x080000000ULL
-#define BAMBOO_RTC_SIZE 0x2000
-
-/* FPGA Registers */
-#define BAMBOO_FPGA_ADDR 0x080002000ULL
-
-#define BAMBOO_FPGA_CONFIG2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x1)
-#define BAMBOO_FULL_DUPLEX_EN(x) (x & 0x08)
-#define BAMBOO_FORCE_100Mbps(x) (x & 0x04)
-#define BAMBOO_AUTONEGOTIATE(x) (x & 0x02)
-
-#define BAMBOO_FPGA_SETTING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x3)
-#define BAMBOO_BOOT_SMALL_FLASH(x) (!(x & 0x80))
-#define BAMBOO_LARGE_FLASH_EN(x) (!(x & 0x40))
-#define BAMBOO_BOOT_NAND_FLASH(x) (!(x & 0x20))
-
-#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4)
-#define BAMBOO_SEL_MII(x) (x & 0x80)
-#define BAMBOO_SEL_RMII(x) (x & 0x40)
-#define BAMBOO_SEL_SMII(x) (x & 0x20)
-
-/* Flash */
-#define BAMBOO_SMALL_FLASH_LOW 0x087f00000ULL
-#define BAMBOO_SMALL_FLASH_HIGH 0x0fff00000ULL
-#define BAMBOO_SMALL_FLASH_SIZE 0x100000
-#define BAMBOO_LARGE_FLASH_LOW 0x087800000ULL
-#define BAMBOO_LARGE_FLASH_HIGH1 0x0ff800000ULL
-#define BAMBOO_LARGE_FLASH_HIGH2 0x0ffc00000ULL
-#define BAMBOO_LARGE_FLASH_SIZE 0x400000
-#define BAMBOO_SRAM_LOW 0x087f00000ULL
-#define BAMBOO_SRAM_HIGH1 0x0fff00000ULL
-#define BAMBOO_SRAM_HIGH2 0x0ff800000ULL
-#define BAMBOO_SRAM_SIZE 0x100000
-#define BAMBOO_NAND_FLASH_REG_ADDR 0x090000000ULL
-#define BAMBOO_NAND_FLASH_REG_SIZE 0x2000
-
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE 4
-
-#define UART0_IO_BASE 0xEF600300
-#define UART1_IO_BASE 0xEF600400
-#define UART2_IO_BASE 0xEF600500
-#define UART3_IO_BASE 0xEF600600
-
-#define BASE_BAUD 33177600/3/16
-#define UART0_INT 0
-#define UART1_INT 1
-#define UART2_INT 3
-#define UART3_INT 4
-
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (void*)UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1) \
- STD_UART_OP(2) \
- STD_UART_OP(3)
-
-/* PCI support */
-#define BAMBOO_PCI_CFGA_PLB32 0xeec00000
-#define BAMBOO_PCI_CFGD_PLB32 0xeec00004
-
-#define BAMBOO_PCI_IO_BASE 0x00000000e8000000ULL
-#define BAMBOO_PCI_IO_SIZE 0x00010000
-#define BAMBOO_PCI_MEM_OFFSET 0x00000000
-#define BAMBOO_PCI_PHY_MEM_BASE 0x00000000a0000000ULL
-
-#define BAMBOO_PCI_LOWER_IO 0x00000000
-#define BAMBOO_PCI_UPPER_IO 0x0000ffff
-#define BAMBOO_PCI_LOWER_MEM 0xa0000000
-#define BAMBOO_PCI_UPPER_MEM 0xafffffff
-#define BAMBOO_PCI_MEM_BASE 0xa0000000
-
-#define BAMBOO_PCIL0_BASE 0x00000000ef400000ULL
-#define BAMBOO_PCIL0_SIZE 0x40
-
-#define BAMBOO_PCIL0_PMM0LA 0x000
-#define BAMBOO_PCIL0_PMM0MA 0x004
-#define BAMBOO_PCIL0_PMM0PCILA 0x008
-#define BAMBOO_PCIL0_PMM0PCIHA 0x00C
-#define BAMBOO_PCIL0_PMM1LA 0x010
-#define BAMBOO_PCIL0_PMM1MA 0x014
-#define BAMBOO_PCIL0_PMM1PCILA 0x018
-#define BAMBOO_PCIL0_PMM1PCIHA 0x01C
-#define BAMBOO_PCIL0_PMM2LA 0x020
-#define BAMBOO_PCIL0_PMM2MA 0x024
-#define BAMBOO_PCIL0_PMM2PCILA 0x028
-#define BAMBOO_PCIL0_PMM2PCIHA 0x02C
-#define BAMBOO_PCIL0_PTM1MS 0x030
-#define BAMBOO_PCIL0_PTM1LA 0x034
-#define BAMBOO_PCIL0_PTM2MS 0x038
-#define BAMBOO_PCIL0_PTM2LA 0x03C
-
-#endif /* __ASM_BAMBOO_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/bubinga.c b/arch/ppc/platforms/4xx/bubinga.c
deleted file mode 100644
index cd696be55aca..000000000000
--- a/arch/ppc/platforms/4xx/bubinga.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * Support for IBM PPC 405EP evaluation board (Bubinga).
- *
- * Author: SAW (IBM), derived from walnut.c.
- * Maintained by MontaVista Software <source@mvista.com>
- *
- * 2003 (c) MontaVista Softare Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/blkdev.h>
-#include <linux/pci.h>
-#include <linux/rtc.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pci-bridge.h>
-#include <asm/processor.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/io.h>
-#include <asm/todc.h>
-#include <asm/kgdb.h>
-#include <asm/ocp.h>
-#include <asm/ibm_ocp_pci.h>
-
-#include <platforms/4xx/ibm405ep.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-extern bd_t __res;
-
-void *bubinga_rtc_base;
-
-/* Some IRQs unique to the board
- * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
- */
-int __init
-ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
- {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
- {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
- {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
- };
-
- const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-};
-
-/* The serial clock for the chip is an internal clock determined by
- * different clock speeds/dividers.
- * Calculate the proper input baud rate and setup the serial driver.
- */
-static void __init
-bubinga_early_serial_map(void)
-{
- u32 uart_div;
- int uart_clock;
- struct uart_port port;
-
- /* Calculate the serial clock input frequency
- *
- * The base baud is the PLL OUTA (provided in the board info
- * structure) divided by the external UART Divisor, divided
- * by 16.
- */
- uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
- uart_clock = __res.bi_procfreq / uart_div;
-
- /* Setup serial port access */
- memset(&port, 0, sizeof(port));
- port.membase = (void*)ACTING_UART0_IO_BASE;
- port.irq = ACTING_UART0_INT;
- port.uartclk = uart_clock;
- port.regshift = 0;
- port.iotype = UPIO_MEM;
- port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- port.line = 0;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 0 failed\n");
- }
-
- port.membase = (void*)ACTING_UART1_IO_BASE;
- port.irq = ACTING_UART1_INT;
- port.line = 1;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 1 failed\n");
- }
-}
-
-void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
-
- unsigned int bar_response, bar;
- /*
- * Expected PCI mapping:
- *
- * PLB addr PCI memory addr
- * --------------------- ---------------------
- * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
- * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
- *
- * PLB addr PCI io addr
- * --------------------- ---------------------
- * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
- *
- * The following code is simplified by assuming that the bootrom
- * has been well behaved in following this mapping.
- */
-
-#ifdef DEBUG
- int i;
-
- printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
- printk("PCI bridge regs before fixup \n");
- for (i = 0; i <= 3; i++) {
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
- }
- printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
- printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
- printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
- printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-
- /* added for IBM boot rom version 1.15 bios bar changes -AK */
-
- /* Disable region first */
- out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
- /* PLB starting addr, PCI: 0x80000000 */
- out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
- /* PCI start addr, 0x80000000 */
- out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
- /* 512MB range of PLB to PCI */
- out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
- /* Enable no pre-fetch, enable region */
- out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
- (PPC405_PCI_UPPER_MEM -
- PPC405_PCI_MEM_BASE)) | 0x01));
-
- /* Disable region one */
- out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
- out_le32((void *) &(pcip->ptm1ms), 0x00000001);
-
- /* Disable region two */
- out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
- out_le32((void *) &(pcip->ptm2ms), 0x00000000);
- out_le32((void *) &(pcip->ptm2la), 0x00000000);
-
- /* Zero config bars */
- for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
- early_write_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- 0x00000000);
- early_read_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- &bar_response);
- DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
- hose->first_busno, PCI_SLOT(hose->first_busno),
- PCI_FUNC(hose->first_busno), bar, bar_response);
- }
- /* end workaround */
-
-#ifdef DEBUG
- printk("PCI bridge regs after fixup \n");
- for (i = 0; i <= 3; i++) {
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
- }
- printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
- printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
- printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
- printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-#endif
-}
-
-void __init
-bubinga_setup_arch(void)
-{
- ppc4xx_setup_arch();
-
- ibm_ocp_set_emac(0, 1);
-
- bubinga_early_serial_map();
-
- /* RTC step for the evb405ep */
- bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR;
- TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base,
- bubinga_rtc_base, 8);
- /* Identify the system */
- printk("IBM Bubinga port (MontaVista Software, Inc. <source@mvista.com>)\n");
-}
-
-void __init
-bubinga_map_io(void)
-{
- ppc4xx_map_io();
- io_block_mapping(BUBINGA_RTC_VADDR,
- BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
-{
- ppc4xx_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = bubinga_setup_arch;
- ppc_md.setup_io_mappings = bubinga_map_io;
-
-#ifdef CONFIG_GEN_RTC
- ppc_md.time_init = todc_time_init;
- ppc_md.set_rtc_time = todc_set_rtc_time;
- ppc_md.get_rtc_time = todc_get_rtc_time;
- ppc_md.nvram_read_val = todc_direct_read_val;
- ppc_md.nvram_write_val = todc_direct_write_val;
-#endif
-#ifdef CONFIG_KGDB
- ppc_md.early_serial_map = bubinga_early_serial_map;
-#endif
-}
-
diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h
deleted file mode 100644
index 5c408060eb35..000000000000
--- a/arch/ppc/platforms/4xx/bubinga.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Bubinga board definitions
- *
- * Copyright (c) 2005 DENX Software Engineering
- * Stefan Roese <sr@denx.de>
- *
- * Based on original work by
- * SAW (IBM)
- * 2003 (c) MontaVista Softare Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __BUBINGA_H__
-#define __BUBINGA_H__
-
-#include <platforms/4xx/ibm405ep.h>
-#include <asm/ppcboot.h>
-
-/* Memory map for the Bubinga board.
- * Generic 4xx plus RTC.
- */
-
-#define BUBINGA_RTC_PADDR ((uint)0xf0000000)
-#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR
-#define BUBINGA_RTC_SIZE ((uint)8*1024)
-
-/* The UART clock is based off an internal clock -
- * define BASE_BAUD based on the internal clock and divider(s).
- * Since BASE_BAUD must be a constant, we will initialize it
- * using clock/divider values which OpenBIOS initializes
- * for typical configurations at various CPU speeds.
- * The base baud is calculated as (FWDA / EXT UART DIV / 16)
- */
-#define BASE_BAUD 0
-
-/* Flash */
-#define PPC40x_FPGA_BASE 0xF0300000
-#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */
-#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
-#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
-#define PPC40x_FLASH_LOW 0xFFF00000
-#define PPC40x_FLASH_HIGH 0xFFF80000
-#define PPC40x_FLASH_SIZE 0x80000
-
-#define PPC4xx_MACHINE_NAME "IBM Bubinga"
-
-#endif /* __BUBINGA_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/cpci405.c b/arch/ppc/platforms/4xx/cpci405.c
deleted file mode 100644
index 2e7e25dd84cb..000000000000
--- a/arch/ppc/platforms/4xx/cpci405.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Board setup routines for the esd CPCI-405 cPCI Board.
- *
- * Copyright 2001-2006 esd electronic system design - hannover germany
- *
- * Authors: Matthias Fuchs
- * matthias.fuchs@esd-electronics.com
- * Stefan Roese
- * stefan.roese@esd-electronics.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <asm/system.h>
-#include <asm/pci-bridge.h>
-#include <asm/machdep.h>
-#include <asm/todc.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <asm/ocp.h>
-#include <asm/ibm_ocp_pci.h>
-#include <platforms/4xx/ibm405gp.h>
-
-#ifdef CONFIG_GEN_RTC
-void *cpci405_nvram;
-#endif
-
-extern bd_t __res;
-
-/*
- * Some IRQs unique to CPCI-405.
- */
-int __init
-ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- {28, 29, 30, 27}, /* IDSEL 15 - cPCI slot 8 */
- {29, 30, 27, 28}, /* IDSEL 16 - cPCI slot 7 */
- {30, 27, 28, 29}, /* IDSEL 17 - cPCI slot 6 */
- {27, 28, 29, 30}, /* IDSEL 18 - cPCI slot 5 */
- {28, 29, 30, 27}, /* IDSEL 19 - cPCI slot 4 */
- {29, 30, 27, 28}, /* IDSEL 20 - cPCI slot 3 */
- {30, 27, 28, 29}, /* IDSEL 21 - cPCI slot 2 */
- };
- const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-};
-
-/* The serial clock for the chip is an internal clock determined by
- * different clock speeds/dividers.
- * Calculate the proper input baud rate and setup the serial driver.
- */
-static void __init
-cpci405_early_serial_map(void)
-{
- u32 uart_div;
- int uart_clock;
- struct uart_port port;
-
- /* Calculate the serial clock input frequency
- *
- * The uart clock is the cpu frequency (provided in the board info
- * structure) divided by the external UART Divisor.
- */
- uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
- uart_clock = __res.bi_procfreq / uart_div;
-
- /* Setup serial port access */
- memset(&port, 0, sizeof(port));
-#if defined(CONFIG_UART0_TTYS0)
- port.membase = (void*)UART0_IO_BASE;
- port.irq = UART0_INT;
-#else
- port.membase = (void*)UART1_IO_BASE;
- port.irq = UART1_INT;
-#endif
- port.uartclk = uart_clock;
- port.regshift = 0;
- port.iotype = UPIO_MEM;
- port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- port.line = 0;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 0 failed\n");
- }
-#if defined(CONFIG_UART0_TTYS0)
- port.membase = (void*)UART1_IO_BASE;
- port.irq = UART1_INT;
-#else
- port.membase = (void*)UART0_IO_BASE;
- port.irq = UART0_INT;
-#endif
- port.line = 1;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 1 failed\n");
- }
-}
-
-void __init
-cpci405_setup_arch(void)
-{
- ppc4xx_setup_arch();
-
- ibm_ocp_set_emac(0, 0);
-
- cpci405_early_serial_map();
-
-#ifdef CONFIG_GEN_RTC
- TODC_INIT(TODC_TYPE_MK48T35,
- cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
-#endif
-}
-
-void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
- unsigned int bar_response, bar;
-
- /* Disable region first */
- out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
- /* PLB starting addr, PCI: 0x80000000 */
- out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
- /* PCI start addr, 0x80000000 */
- out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
- /* 512MB range of PLB to PCI */
- out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
- /* Enable no pre-fetch, enable region */
- out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
- (PPC405_PCI_UPPER_MEM -
- PPC405_PCI_MEM_BASE)) | 0x01));
-
- /* Disable region one */
- out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
- out_le32((void *) &(pcip->ptm1ms), 0x00000001);
-
- /* Disable region two */
- out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
- out_le32((void *) &(pcip->ptm2ms), 0x00000000);
- out_le32((void *) &(pcip->ptm2la), 0x00000000);
-
- /* Zero config bars */
- for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
- early_write_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- 0x00000000);
- early_read_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- &bar_response);
- }
-#endif
-}
-
-void __init
-cpci405_map_io(void)
-{
- ppc4xx_map_io();
-
-#ifdef CONFIG_GEN_RTC
- cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
-#endif
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
-{
- ppc4xx_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = cpci405_setup_arch;
- ppc_md.setup_io_mappings = cpci405_map_io;
-
-#ifdef CONFIG_GEN_RTC
- ppc_md.time_init = todc_time_init;
- ppc_md.set_rtc_time = todc_set_rtc_time;
- ppc_md.get_rtc_time = todc_get_rtc_time;
- ppc_md.nvram_read_val = todc_direct_read_val;
- ppc_md.nvram_write_val = todc_direct_write_val;
-#endif
-}
diff --git a/arch/ppc/platforms/4xx/cpci405.h b/arch/ppc/platforms/4xx/cpci405.h
deleted file mode 100644
index a6c0a138b0d7..000000000000
--- a/arch/ppc/platforms/4xx/cpci405.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * CPCI-405 board specific definitions
- *
- * Copyright 2001-2006 esd electronic system design - hannover germany
- *
- * Authors: Matthias Fuchs
- * matthias.fuchs@esd-electronics.com
- * Stefan Roese
- * stefan.roese@esd-electronics.com
- */
-
-#ifdef __KERNEL__
-#ifndef __CPCI405_H__
-#define __CPCI405_H__
-
-#include <platforms/4xx/ibm405gp.h>
-#include <asm/ppcboot.h>
-
-/* Map for the NVRAM space */
-#define CPCI405_NVRAM_PADDR ((uint)0xf0200000)
-#define CPCI405_NVRAM_SIZE ((uint)32*1024)
-
-#define BASE_BAUD 0
-
-#define PPC4xx_MACHINE_NAME "esd CPCI-405"
-
-#endif /* __CPCI405_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
deleted file mode 100644
index 8027a36fc5bb..000000000000
--- a/arch/ppc/platforms/4xx/ebony.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * Ebony board specific routines
- *
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2002-2005 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003-2005 Zultys Technologies
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/pci-bridge.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/ppcboot.h>
-#include <asm/tlbflush.h>
-
-#include <syslib/gen550.h>
-#include <syslib/ibm440gp_common.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-/*
- * Ebony external IRQ triggering/polarity settings
- */
-unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */
-};
-
-static void __init
-ebony_calibrate_decr(void)
-{
- unsigned int freq;
-
- /*
- * Determine system clock speed
- *
- * If we are on Rev. B silicon, then use
- * default external system clock. If we are
- * on Rev. C silicon then errata forces us to
- * use the internal clock.
- */
- if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0)
- freq = EBONY_440GP_RB_SYSCLK;
- else
- freq = EBONY_440GP_RC_SYSCLK;
-
- ibm44x_calibrate_decr(freq);
-}
-
-static int
-ebony_show_cpuinfo(struct seq_file *m)
-{
- seq_printf(m, "vendor\t\t: IBM\n");
- seq_printf(m, "machine\t\t: Ebony\n");
-
- return 0;
-}
-
-static inline int
-ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
- { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
- { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
- { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
- };
-
- const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-}
-
-#define PCIX_WRITEL(value, offset) \
- (writel(value, pcix_reg_base + offset))
-
-/*
- * FIXME: This is only here to "make it work". This will move
- * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
- * configuration library. -Matt
- */
-static void __init
-ebony_setup_pcix(void)
-{
- void __iomem *pcix_reg_base;
-
- pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
-
- /* Disable all windows */
- PCIX_WRITEL(0, PCIX0_POM0SA);
- PCIX_WRITEL(0, PCIX0_POM1SA);
- PCIX_WRITEL(0, PCIX0_POM2SA);
- PCIX_WRITEL(0, PCIX0_PIM0SA);
- PCIX_WRITEL(0, PCIX0_PIM1SA);
- PCIX_WRITEL(0, PCIX0_PIM2SA);
-
- /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
- PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
- PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
- PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
- PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
- PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
-
- /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
- PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
- PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
- PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
-
- eieio();
-}
-
-static void __init
-ebony_setup_hose(void)
-{
- struct pci_controller *hose;
-
- /* Configure windows on the PCI-X host bridge */
- ebony_setup_pcix();
-
- hose = pcibios_alloc_controller();
-
- if (!hose)
- return;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
-
- pci_init_resource(&hose->io_resource,
- EBONY_PCI_LOWER_IO,
- EBONY_PCI_UPPER_IO,
- IORESOURCE_IO,
- "PCI host bridge");
-
- pci_init_resource(&hose->mem_resources[0],
- EBONY_PCI_LOWER_MEM,
- EBONY_PCI_UPPER_MEM,
- IORESOURCE_MEM,
- "PCI host bridge");
-
- hose->io_space.start = EBONY_PCI_LOWER_IO;
- hose->io_space.end = EBONY_PCI_UPPER_IO;
- hose->mem_space.start = EBONY_PCI_LOWER_MEM;
- hose->mem_space.end = EBONY_PCI_UPPER_MEM;
- hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
- isa_io_base = (unsigned long)hose->io_base_virt;
-
- setup_indirect_pci(hose,
- EBONY_PCI_CFGA_PLB32,
- EBONY_PCI_CFGD_PLB32);
- hose->set_cfg_type = 1;
-
- hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
- ppc_md.pci_swizzle = common_swizzle;
- ppc_md.pci_map_irq = ebony_map_irq;
-}
-
-TODC_ALLOC();
-
-static void __init
-ebony_early_serial_map(void)
-{
- struct uart_port port;
-
- /* Setup ioremapped serial port access */
- memset(&port, 0, sizeof(port));
- port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
- port.irq = 0;
- port.uartclk = clocks.uart0;
- port.regshift = 0;
- port.iotype = UPIO_MEM;
- port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- port.line = 0;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 0 failed\n");
- }
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- /* Configure debug serial access */
- gen550_init(0, &port);
-
- /* Purge TLB entry added in head_44x.S for early serial access */
- _tlbie(UART0_IO_BASE, 0);
-#endif
-
- port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
- port.irq = 1;
- port.uartclk = clocks.uart1;
- port.line = 1;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 1 failed\n");
- }
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- /* Configure debug serial access */
- gen550_init(1, &port);
-#endif
-}
-
-static void __init
-ebony_setup_arch(void)
-{
- struct ocp_def *def;
- struct ocp_func_emac_data *emacdata;
-
- /* Set mac_addr for each EMAC */
- def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
- emacdata = def->additions;
- emacdata->phy_map = 0x00000001; /* Skip 0x00 */
- emacdata->phy_mode = PHY_MODE_RMII;
- memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
-
- def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
- emacdata = def->additions;
- emacdata->phy_map = 0x00000001; /* Skip 0x00 */
- emacdata->phy_mode = PHY_MODE_RMII;
- memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
-
- /*
- * Determine various clocks.
- * To be completely correct we should get SysClk
- * from FPGA, because it can be changed by on-board switches
- * --ebs
- */
- ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
- ocp_sys_info.opb_bus_freq = clocks.opb;
-
- /* Setup TODC access */
- TODC_INIT(TODC_TYPE_DS1743,
- 0,
- 0,
- ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
- 8);
-
- /* init to some ~sane value until calibrate_delay() runs */
- loops_per_jiffy = 50000000/HZ;
-
- /* Setup PCI host bridge */
- ebony_setup_hose();
-
-#ifdef CONFIG_BLK_DEV_INITRD
- if (initrd_start)
- ROOT_DEV = Root_RAM0;
- else
-#endif
-#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
-#else
- ROOT_DEV = Root_HDA1;
-#endif
-
- ebony_early_serial_map();
-
- /* Identify the system */
- printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
- unsigned long r5, unsigned long r6, unsigned long r7)
-{
- ibm44x_platform_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = ebony_setup_arch;
- ppc_md.show_cpuinfo = ebony_show_cpuinfo;
- ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
-
- ppc_md.calibrate_decr = ebony_calibrate_decr;
- ppc_md.time_init = todc_time_init;
- ppc_md.set_rtc_time = todc_set_rtc_time;
- ppc_md.get_rtc_time = todc_get_rtc_time;
-
- ppc_md.nvram_read_val = todc_direct_read_val;
- ppc_md.nvram_write_val = todc_direct_write_val;
-#ifdef CONFIG_KGDB
- ppc_md.early_serial_map = ebony_early_serial_map;
-#endif
-}
-
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
deleted file mode 100644
index f40e33d39d76..000000000000
--- a/arch/ppc/platforms/4xx/ebony.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Ebony board definitions
- *
- * Matt Porter <mporter@mvista.com>
- *
- * Copyright 2002 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_EBONY_H__
-#define __ASM_EBONY_H__
-
-#include <platforms/4xx/ibm440gp.h>
-
-/* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0 0xE0000800
-
-/* Where to find the MAC info */
-#define OPENBIOS_MAC_BASE 0xfffffe0c
-#define OPENBIOS_MAC_OFFSET 0x0c
-
-/* Default clock rates for Rev. B and Rev. C silicon */
-#define EBONY_440GP_RB_SYSCLK 33000000
-#define EBONY_440GP_RC_SYSCLK 400000000
-
-/* RTC/NVRAM location */
-#define EBONY_RTC_ADDR 0x0000000148000000ULL
-#define EBONY_RTC_SIZE 0x2000
-
-/* Flash */
-#define EBONY_FPGA_ADDR 0x0000000148300000ULL
-#define EBONY_BOOT_SMALL_FLASH(x) (x & 0x20)
-#define EBONY_ONBRD_FLASH_EN(x) (x & 0x02)
-#define EBONY_FLASH_SEL(x) (x & 0x01)
-#define EBONY_SMALL_FLASH_LOW1 0x00000001ff800000ULL
-#define EBONY_SMALL_FLASH_LOW2 0x00000001ff880000ULL
-#define EBONY_SMALL_FLASH_HIGH1 0x00000001fff00000ULL
-#define EBONY_SMALL_FLASH_HIGH2 0x00000001fff80000ULL
-#define EBONY_SMALL_FLASH_SIZE 0x80000
-#define EBONY_LARGE_FLASH_LOW 0x00000001ff800000ULL
-#define EBONY_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
-#define EBONY_LARGE_FLASH_SIZE 0x400000
-
-#define EBONY_SMALL_FLASH_BASE 0x00000001fff80000ULL
-#define EBONY_LARGE_FLASH_BASE 0x00000001ff800000ULL
-
-/*
- * Serial port defines
- */
-
-#if defined(__BOOTER__)
-/* OpenBIOS defined UART mappings, used by bootloader shim */
-#define UART0_IO_BASE 0xE0000200
-#define UART1_IO_BASE 0xE0000300
-#else
-/* head_44x.S created UART mapping, used before early_serial_setup.
- * We cannot use default OpenBIOS UART mappings because they
- * don't work for configurations with more than 512M RAM. --ebs
- */
-#define UART0_IO_BASE 0xF0000200
-#define UART1_IO_BASE 0xF0000300
-#endif
-
-/* external Epson SG-615P */
-#define BASE_BAUD 691200
-
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (void*)UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1)
-
-/* PCI support */
-#define EBONY_PCI_LOWER_IO 0x00000000
-#define EBONY_PCI_UPPER_IO 0x0000ffff
-#define EBONY_PCI_LOWER_MEM 0x80002000
-#define EBONY_PCI_UPPER_MEM 0xffffefff
-
-#define EBONY_PCI_CFGREGS_BASE 0x000000020ec00000
-#define EBONY_PCI_CFGA_PLB32 0x0ec00000
-#define EBONY_PCI_CFGD_PLB32 0x0ec00004
-
-#define EBONY_PCI_IO_BASE 0x0000000208000000ULL
-#define EBONY_PCI_IO_SIZE 0x00010000
-#define EBONY_PCI_MEM_OFFSET 0x00000000
-
-#endif /* __ASM_EBONY_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ep405.c b/arch/ppc/platforms/4xx/ep405.c
deleted file mode 100644
index 5aa295022804..000000000000
--- a/arch/ppc/platforms/4xx/ep405.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Embedded Planet 405GP board
- * http://www.embeddedplanet.com
- *
- * Author: Matthew Locke <mlocke@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <asm/system.h>
-#include <asm/pci-bridge.h>
-#include <asm/machdep.h>
-#include <asm/todc.h>
-#include <asm/ocp.h>
-#include <asm/ibm_ocp_pci.h>
-
-#undef DEBUG
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-u8 *ep405_bcsr;
-u8 *ep405_nvram;
-
-static struct {
- u8 cpld_xirq_select;
- int pci_idsel;
- int irq;
-} ep405_devtable[] = {
-#ifdef CONFIG_EP405PC
- {0x07, 0x0E, 25}, /* EP405PC: USB */
-#endif
-};
-
-int __init
-ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- int i;
-
- /* AFAICT this is only called a few times during PCI setup, so
- performance is not critical */
- for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
- if (idsel == ep405_devtable[i].pci_idsel)
- return ep405_devtable[i].irq;
- }
- return -1;
-};
-
-void __init
-ep405_setup_arch(void)
-{
- ppc4xx_setup_arch();
-
- ibm_ocp_set_emac(0, 0);
-
- if (__res.bi_nvramsize == 512*1024) {
- /* FIXME: we should properly handle NVRTCs of different sizes */
- TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
- }
-}
-
-void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
- unsigned int bar_response, bar;
- /*
- * Expected PCI mapping:
- *
- * PLB addr PCI memory addr
- * --------------------- ---------------------
- * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
- * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
- *
- * PLB addr PCI io addr
- * --------------------- ---------------------
- * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
- *
- */
-
- /* Disable region zero first */
- out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
- /* PLB starting addr, PCI: 0x80000000 */
- out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
- /* PCI start addr, 0x80000000 */
- out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
- /* 512MB range of PLB to PCI */
- out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
- /* Enable no pre-fetch, enable region */
- out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
- (PPC405_PCI_UPPER_MEM -
- PPC405_PCI_MEM_BASE)) | 0x01));
-
- /* Disable region one */
- out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
- out_le32((void *) &(pcip->ptm1ms), 0x00000000);
-
- /* Disable region two */
- out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
- out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
- /* Configure PTM (PCI->PLB) region 1 */
- out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
- /* Disable PTM region 2 */
- out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
- /* Zero config bars */
- for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
- early_write_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- 0x00000000);
- early_read_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- &bar_response);
- DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
- hose->first_busno, PCI_SLOT(hose->first_busno),
- PCI_FUNC(hose->first_busno), bar, bar_response);
- }
- /* end workaround */
-#endif
-}
-
-void __init
-ep405_map_io(void)
-{
- bd_t *bip = &__res;
-
- ppc4xx_map_io();
-
- ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
-
- if (bip->bi_nvramsize > 0) {
- ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize);
- }
-}
-
-void __init
-ep405_init_IRQ(void)
-{
- int i;
-
- ppc4xx_init_IRQ();
-
- /* Workaround for a bug in the firmware it incorrectly sets
- the IRQ polarities for XIRQ0 and XIRQ1 */
- mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
- mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
-
- /* Activate the XIRQs from the CPLD */
- writeb(0xf0, ep405_bcsr+10);
-
- /* Set up IRQ routing */
- for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
- if ( (ep405_devtable[i].irq >= 25)
- && (ep405_devtable[i].irq) <= 31) {
- writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
- writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6);
- }
- }
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
-{
- ppc4xx_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = ep405_setup_arch;
- ppc_md.setup_io_mappings = ep405_map_io;
- ppc_md.init_IRQ = ep405_init_IRQ;
-
- ppc_md.nvram_read_val = todc_direct_read_val;
- ppc_md.nvram_write_val = todc_direct_write_val;
-
- if (__res.bi_nvramsize == 512*1024) {
- ppc_md.time_init = todc_time_init;
- ppc_md.set_rtc_time = todc_set_rtc_time;
- ppc_md.get_rtc_time = todc_get_rtc_time;
- } else {
- printk("EP405: NVRTC size is not 512k (not a DS1557). Not sure what to do with it\n");
- }
-}
diff --git a/arch/ppc/platforms/4xx/ep405.h b/arch/ppc/platforms/4xx/ep405.h
deleted file mode 100644
index 9814fc431725..000000000000
--- a/arch/ppc/platforms/4xx/ep405.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Embedded Planet 405GP board
- * http://www.embeddedplanet.com
- *
- * Author: Matthew Locke <mlocke@mvista.com>
- *
- * 2000 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_EP405_H__
-#define __ASM_EP405_H__
-
-/* We have a 405GP core */
-#include <platforms/4xx/ibm405gp.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-typedef struct board_info {
- unsigned int bi_memsize; /* DRAM installed, in bytes */
- unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
- unsigned int bi_intfreq; /* Processor speed, in Hz */
- unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
- unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
- unsigned int bi_nvramsize; /* Size of the NVRAM/RTC */
-} bd_t;
-
-/* Some 4xx parts use a different timebase frequency from the internal clock.
-*/
-#define bi_tbfreq bi_intfreq
-
-extern u8 *ep405_bcsr;
-extern u8 *ep405_nvram;
-
-/* Map for the BCSR and NVRAM space */
-#define EP405_BCSR_PADDR ((uint)0xf4000000)
-#define EP405_BCSR_SIZE ((uint)16)
-#define EP405_NVRAM_PADDR ((uint)0xf4200000)
-
-/* serial defines */
-#define BASE_BAUD 399193
-
-#define PPC4xx_MACHINE_NAME "Embedded Planet 405GP"
-
-#endif /* !__ASSEMBLY__ */
-#endif /* __ASM_EP405_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c
deleted file mode 100644
index fb3630a1608d..000000000000
--- a/arch/ppc/platforms/4xx/ibm405ep.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Support for IBM PPC 405EP processors.
- *
- * Author: SAW (IBM), derived from ibmnp405l.c.
- * Maintained by MontaVista Software <source@mvista.com>
- *
- * 2003 (c) MontaVista Softare Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-
-#include <asm/ibm4xx.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-#include <platforms/4xx/ibm405ep.h>
-
-static struct ocp_func_mal_data ibm405ep_mal0_def = {
- .num_tx_chans = 4, /* Number of TX channels */
- .num_rx_chans = 2, /* Number of RX channels */
- .txeob_irq = 11, /* TX End Of Buffer IRQ */
- .rxeob_irq = 12, /* RX End Of Buffer IRQ */
- .txde_irq = 13, /* TX Descriptor Error IRQ */
- .rxde_irq = 14, /* RX Descriptor Error IRQ */
- .serr_irq = 10, /* MAL System Error IRQ */
- .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_emac_data ibm405ep_emac0_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = -1, /* ZMII device index */
- .zmii_mux = 0, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 0, /* MAL rx channel number */
- .mal_tx_chan = 0, /* MAL tx channel number */
- .wol_irq = 9, /* WOL interrupt number */
- .mdio_idx = 0, /* MDIO via EMAC0 */
- .tah_idx = -1, /* No TAH */
-};
-
-static struct ocp_func_emac_data ibm405ep_emac1_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = -1, /* ZMII device index */
- .zmii_mux = 0, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 1, /* MAL rx channel number */
- .mal_tx_chan = 2, /* MAL tx channel number */
- .wol_irq = 9, /* WOL interrupt number */
- .mdio_idx = 0, /* MDIO via EMAC0 */
- .tah_idx = -1, /* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_iic_data ibm405ep_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_OPB,
- .index = 0,
- .paddr = 0xEF600000,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = UART0_IO_BASE,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = UART1_IO_BASE,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .paddr = 0xEF600500,
- .irq = 2,
- .pm = IBM_CPM_IIC0,
- .additions = &ibm405ep_iic0_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .paddr = 0xEF600700,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_MAL,
- .paddr = OCP_PADDR_NA,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- .additions = &ibm405ep_mal0_def,
- .show = &ocp_show_mal_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 0,
- .paddr = EMAC0_BASE,
- .irq = 15,
- .pm = OCP_CPM_NA,
- .additions = &ibm405ep_emac0_def,
- .show = &ocp_show_emac_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 1,
- .paddr = 0xEF600900,
- .irq = 17,
- .pm = OCP_CPM_NA,
- .additions = &ibm405ep_emac1_def,
- .show = &ocp_show_emac_data
- },
- { .vendor = OCP_VENDOR_INVALID
- }
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
- { .polarity = 0xffff7f80,
- .triggering = 0x00000000,
- .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
- }
-};
diff --git a/arch/ppc/platforms/4xx/ibm405ep.h b/arch/ppc/platforms/4xx/ibm405ep.h
deleted file mode 100644
index 3ef20a547080..000000000000
--- a/arch/ppc/platforms/4xx/ibm405ep.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * IBM PPC 405EP processor defines.
- *
- * Author: SAW (IBM), derived from ibm405gp.h.
- * Maintained by MontaVista Software <source@mvista.com>
- *
- * 2003 (c) MontaVista Softare Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM405EP_H__
-#define __ASM_IBM405EP_H__
-
-
-/* ibm405.h at bottom of this file */
-
-/* PCI
- * PCI Bridge config reg definitions
- * see 17-19 of manual
- */
-
-#define PPC405_PCI_CONFIG_ADDR 0xeec00000
-#define PPC405_PCI_CONFIG_DATA 0xeec00004
-
-#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
- /* setbat */
-#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
-#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
-#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
-
-#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
-#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
-#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
-#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
-
-#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
-
-#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
-#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
-
-/* serial port defines */
-#define RS_TABLE_SIZE 2
-
-#define UART0_INT 0
-#define UART1_INT 1
-
-#define PCIL0_BASE 0xEF400000
-#define UART0_IO_BASE 0xEF600300
-#define UART1_IO_BASE 0xEF600400
-#define EMAC0_BASE 0xEF600800
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
-
-#if defined(CONFIG_UART0_TTYS0)
-#define ACTING_UART0_IO_BASE UART0_IO_BASE
-#define ACTING_UART1_IO_BASE UART1_IO_BASE
-#define ACTING_UART0_INT UART0_INT
-#define ACTING_UART1_INT UART1_INT
-#else
-#define ACTING_UART0_IO_BASE UART1_IO_BASE
-#define ACTING_UART1_IO_BASE UART0_IO_BASE
-#define ACTING_UART0_INT UART1_INT
-#define ACTING_UART1_INT UART0_INT
-#endif
-
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, ACTING_UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (u8 *)ACTING_UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#define SERIAL_DEBUG_IO_BASE ACTING_UART0_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1)
-
-/* DCR defines */
-#define DCRN_CPMSR_BASE 0x0BA
-#define DCRN_CPMFR_BASE 0x0B9
-
-#define DCRN_CPC0_PLLMR0_BASE 0x0F0
-#define DCRN_CPC0_BOOT_BASE 0x0F1
-#define DCRN_CPC0_CR1_BASE 0x0F2
-#define DCRN_CPC0_EPRCSR_BASE 0x0F3
-#define DCRN_CPC0_PLLMR1_BASE 0x0F4
-#define DCRN_CPC0_UCR_BASE 0x0F5
-#define DCRN_CPC0_UCR_U0DIV 0x07F
-#define DCRN_CPC0_SRR_BASE 0x0F6
-#define DCRN_CPC0_JTAGID_BASE 0x0F7
-#define DCRN_CPC0_SPARE_BASE 0x0F8
-#define DCRN_CPC0_PCI_BASE 0x0F9
-
-
-#define IBM_CPM_GPT 0x80000000 /* GPT interface */
-#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
-#define IBM_CPM_UIC 0x00010000 /* Universal Int Controller */
-#define IBM_CPM_CPU 0x00008000 /* processor core */
-#define IBM_CPM_EBC 0x00002000 /* EBC controller */
-#define IBM_CPM_SDRAM0 0x00004000 /* SDRAM memory controller */
-#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO */
-#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
-#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
-#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
-#define IBM_CPM_DMA 0x00000040 /* DMA controller */
-#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
-#define IBM_CPM_UART1 0x00000002 /* serial port 0 */
-#define IBM_CPM_UART0 0x00000001 /* serial port 1 */
-#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
- | IBM_CPM_OPB | IBM_CPM_EBC \
- | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
- | IBM_CPM_UIC | IBM_CPM_TMRCLK)
-#define DCRN_DMA0_BASE 0x100
-#define DCRN_DMA1_BASE 0x108
-#define DCRN_DMA2_BASE 0x110
-#define DCRN_DMA3_BASE 0x118
-#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
-#define DCRN_DMASR_BASE 0x120
-#define DCRN_EBC_BASE 0x012
-#define DCRN_DCP0_BASE 0x014
-#define DCRN_MAL_BASE 0x180
-#define DCRN_OCM0_BASE 0x018
-#define DCRN_PLB0_BASE 0x084
-#define DCRN_PLLMR_BASE 0x0B0
-#define DCRN_POB0_BASE 0x0A0
-#define DCRN_SDRAM0_BASE 0x010
-#define DCRN_UIC0_BASE 0x0C0
-#define UIC0 DCRN_UIC0_BASE
-
-#include <asm/ibm405.h>
-
-#endif /* __ASM_IBM405EP_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405gp.c b/arch/ppc/platforms/4xx/ibm405gp.c
deleted file mode 100644
index 2ac67a2f0ba6..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gp.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- *
- * Copyright 2000-2001 MontaVista Software Inc.
- * Original author: Armin Kuster akuster@mvista.com
- *
- * Module name: ibm405gp.c
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <platforms/4xx/ibm405gp.h>
-#include <asm/ibm4xx.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ibm405gp_emac0_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = -1, /* ZMII device index */
- .zmii_mux = 0, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 0, /* MAL rx channel number */
- .mal_tx_chan = 0, /* MAL tx channel number */
- .wol_irq = 9, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm405gp_mal0_def = {
- .num_tx_chans = 1, /* Number of TX channels */
- .num_rx_chans = 1, /* Number of RX channels */
- .txeob_irq = 11, /* TX End Of Buffer IRQ */
- .rxeob_irq = 12, /* RX End Of Buffer IRQ */
- .txde_irq = 13, /* TX Descriptor Error IRQ */
- .rxde_irq = 14, /* RX Descriptor Error IRQ */
- .serr_irq = 10, /* MAL System Error IRQ */
- .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm405gp_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_OPB,
- .index = 0,
- .paddr = 0xEF600000,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = UART0_IO_BASE,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = UART1_IO_BASE,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .paddr = 0xEF600500,
- .irq = 2,
- .pm = IBM_CPM_IIC0,
- .additions = &ibm405gp_iic0_def,
- .show = &ocp_show_iic_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .paddr = 0xEF600700,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_MAL,
- .paddr = OCP_PADDR_NA,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- .additions = &ibm405gp_mal0_def,
- .show = &ocp_show_mal_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 0,
- .paddr = EMAC0_BASE,
- .irq = 15,
- .pm = IBM_CPM_EMAC0,
- .additions = &ibm405gp_emac0_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_INVALID
- }
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
- { .polarity = 0xffffff80,
- .triggering = 0x10000000,
- .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
- }
-};
diff --git a/arch/ppc/platforms/4xx/ibm405gp.h b/arch/ppc/platforms/4xx/ibm405gp.h
deleted file mode 100644
index 9f15e5518719..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gp.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Author: Armin Kuster akuster@mvista.com
- *
- * 2001 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM405GP_H__
-#define __ASM_IBM405GP_H__
-
-
-/* ibm405.h at bottom of this file */
-
-/* PCI
- * PCI Bridge config reg definitions
- * see 17-19 of manual
- */
-
-#define PPC405_PCI_CONFIG_ADDR 0xeec00000
-#define PPC405_PCI_CONFIG_DATA 0xeec00004
-
-#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
- /* setbat */
-#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
-#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
-#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
-
-#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
-#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
-#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
-#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
-
-#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
-
-#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
-#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
-
-/* serial port defines */
-#define RS_TABLE_SIZE 2
-
-#define UART0_INT 0
-#define UART1_INT 1
-
-#define PCIL0_BASE 0xEF400000
-#define UART0_IO_BASE 0xEF600300
-#define UART1_IO_BASE 0xEF600400
-#define EMAC0_BASE 0xEF600800
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
-
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (u8 *)UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1)
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(1) \
- STD_UART_OP(0)
-#endif
-
-/* DCR defines */
-#define DCRN_CHCR_BASE 0x0B1
-#define DCRN_CHPSR_BASE 0x0B4
-#define DCRN_CPMSR_BASE 0x0B8
-#define DCRN_CPMFR_BASE 0x0BA
-
-#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */
-#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */
-#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */
-#define CHR1_CETE 0x00800000 /* CPU external timer enable */
-
-#define DCRN_CHPSR_BASE 0x0B4
-#define PSR_PLL_FWD_MASK 0xC0000000
-#define PSR_PLL_FDBACK_MASK 0x30000000
-#define PSR_PLL_TUNING_MASK 0x0E000000
-#define PSR_PLB_CPU_MASK 0x01800000
-#define PSR_OPB_PLB_MASK 0x00600000
-#define PSR_PCI_PLB_MASK 0x00180000
-#define PSR_EB_PLB_MASK 0x00060000
-#define PSR_ROM_WIDTH_MASK 0x00018000
-#define PSR_ROM_LOC 0x00004000
-#define PSR_PCI_ASYNC_EN 0x00001000
-#define PSR_PCI_ARBIT_EN 0x00000400
-
-#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
-#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
-#define IBM_CPM_CPU 0x20000000 /* processor core */
-#define IBM_CPM_DMA 0x10000000 /* DMA controller */
-#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */
-#define IBM_CPM_DCP 0x04000000 /* CodePack */
-#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
-#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
-#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
-#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
-#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
-#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
-#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
-#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */
-#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
- | IBM_CPM_OPB | IBM_CPM_EBC \
- | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
- | IBM_CPM_UIC | IBM_CPM_TMRCLK)
-
-#define DCRN_DMA0_BASE 0x100
-#define DCRN_DMA1_BASE 0x108
-#define DCRN_DMA2_BASE 0x110
-#define DCRN_DMA3_BASE 0x118
-#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
-#define DCRN_DMASR_BASE 0x120
-#define DCRN_EBC_BASE 0x012
-#define DCRN_DCP0_BASE 0x014
-#define DCRN_MAL_BASE 0x180
-#define DCRN_OCM0_BASE 0x018
-#define DCRN_PLB0_BASE 0x084
-#define DCRN_PLLMR_BASE 0x0B0
-#define DCRN_POB0_BASE 0x0A0
-#define DCRN_SDRAM0_BASE 0x010
-#define DCRN_UIC0_BASE 0x0C0
-#define UIC0 DCRN_UIC0_BASE
-
-#include <asm/ibm405.h>
-
-#endif /* __ASM_IBM405GP_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c
deleted file mode 100644
index 9f4dacffdbb3..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gpr.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <platforms/4xx/ibm405gpr.h>
-#include <asm/ibm4xx.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ibm405gpr_emac0_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = -1, /* ZMII device index */
- .zmii_mux = 0, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 0, /* MAL rx channel number */
- .mal_tx_chan = 0, /* MAL tx channel number */
- .wol_irq = 9, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm405gpr_mal0_def = {
- .num_tx_chans = 1, /* Number of TX channels */
- .num_rx_chans = 1, /* Number of RX channels */
- .txeob_irq = 11, /* TX End Of Buffer IRQ */
- .rxeob_irq = 12, /* RX End Of Buffer IRQ */
- .txde_irq = 13, /* TX Descriptor Error IRQ */
- .rxde_irq = 14, /* RX Descriptor Error IRQ */
- .serr_irq = 10, /* MAL System Error IRQ */
- .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm405gpr_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_OPB,
- .index = 0,
- .paddr = 0xEF600000,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = UART0_IO_BASE,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = UART1_IO_BASE,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .paddr = 0xEF600500,
- .irq = 2,
- .pm = IBM_CPM_IIC0,
- .additions = &ibm405gpr_iic0_def,
- .show = &ocp_show_iic_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .paddr = 0xEF600700,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_MAL,
- .paddr = OCP_PADDR_NA,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- .additions = &ibm405gpr_mal0_def,
- .show = &ocp_show_mal_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 0,
- .paddr = EMAC0_BASE,
- .irq = 15,
- .pm = IBM_CPM_EMAC0,
- .additions = &ibm405gpr_emac0_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_INVALID
- }
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
- { .polarity = 0xffffe000,
- .triggering = 0x10000000,
- .ext_irq_mask = 0x00001fff, /* IRQ7 - IRQ12, IRQ0 - IRQ6 */
- }
-};
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.h b/arch/ppc/platforms/4xx/ibm405gpr.h
deleted file mode 100644
index 9e01f1515de3..000000000000
--- a/arch/ppc/platforms/4xx/ibm405gpr.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM405GPR_H__
-#define __ASM_IBM405GPR_H__
-
-
-/* ibm405.h at bottom of this file */
-
-/* PCI
- * PCI Bridge config reg definitions
- * see 17-19 of manual
- */
-
-#define PPC405_PCI_CONFIG_ADDR 0xeec00000
-#define PPC405_PCI_CONFIG_DATA 0xeec00004
-
-#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
- /* setbat */
-#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
-#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
-#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
-
-#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
-#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
-#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
-#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
-
-#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
-
-#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
-#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
-
-/* serial port defines */
-#define RS_TABLE_SIZE 2
-
-#define UART0_INT 0
-#define UART1_INT 1
-
-#define PCIL0_BASE 0xEF400000
-#define UART0_IO_BASE 0xEF600300
-#define UART1_IO_BASE 0xEF600400
-#define EMAC0_BASE 0xEF600800
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
-
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (u8 *)UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1)
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(1) \
- STD_UART_OP(0)
-#endif
-
-/* DCR defines */
-#define DCRN_CHCR_BASE 0x0B1
-#define DCRN_CHPSR_BASE 0x0B4
-#define DCRN_CPMSR_BASE 0x0B8
-#define DCRN_CPMFR_BASE 0x0BA
-
-#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */
-#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */
-#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */
-#define CHR1_CETE 0x00800000 /* CPU external timer enable */
-
-#define DCRN_CHPSR_BASE 0x0B4
-#define PSR_PLL_FWD_MASK 0xC0000000
-#define PSR_PLL_FDBACK_MASK 0x30000000
-#define PSR_PLL_TUNING_MASK 0x0E000000
-#define PSR_PLB_CPU_MASK 0x01800000
-#define PSR_OPB_PLB_MASK 0x00600000
-#define PSR_PCI_PLB_MASK 0x00180000
-#define PSR_EB_PLB_MASK 0x00060000
-#define PSR_ROM_WIDTH_MASK 0x00018000
-#define PSR_ROM_LOC 0x00004000
-#define PSR_PCI_ASYNC_EN 0x00001000
-#define PSR_PCI_ARBIT_EN 0x00000400
-
-#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
-#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
-#define IBM_CPM_CPU 0x20000000 /* processor core */
-#define IBM_CPM_DMA 0x10000000 /* DMA controller */
-#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */
-#define IBM_CPM_DCP 0x04000000 /* CodePack */
-#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
-#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
-#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
-#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
-#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
-#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
-#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
-#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */
-#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
- | IBM_CPM_OPB | IBM_CPM_EBC \
- | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
- | IBM_CPM_UIC | IBM_CPM_TMRCLK)
-
-#define DCRN_DMA0_BASE 0x100
-#define DCRN_DMA1_BASE 0x108
-#define DCRN_DMA2_BASE 0x110
-#define DCRN_DMA3_BASE 0x118
-#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
-#define DCRN_DMASR_BASE 0x120
-#define DCRN_EBC_BASE 0x012
-#define DCRN_DCP0_BASE 0x014
-#define DCRN_MAL_BASE 0x180
-#define DCRN_OCM0_BASE 0x018
-#define DCRN_PLB0_BASE 0x084
-#define DCRN_PLLMR_BASE 0x0B0
-#define DCRN_POB0_BASE 0x0A0
-#define DCRN_SDRAM0_BASE 0x010
-#define DCRN_UIC0_BASE 0x0C0
-#define UIC0 DCRN_UIC0_BASE
-
-#include <asm/ibm405.h>
-
-#endif /* __ASM_IBM405GPR_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c
deleted file mode 100644
index 0de91532aabb..000000000000
--- a/arch/ppc/platforms/4xx/ibm440ep.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * PPC440EP I/O descriptions
- *
- * Wade Farnsworth <wfarnsworth@mvista.com>
- * Copyright 2004 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <platforms/4xx/ibm440ep.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ibm440ep_emac0_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 0, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 0, /* MAL rx channel number */
- .mal_tx_chan = 0, /* MAL tx channel number */
- .wol_irq = 61, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-
-static struct ocp_func_emac_data ibm440ep_emac1_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 1, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 1, /* MAL rx channel number */
- .mal_tx_chan = 2, /* MAL tx channel number */
- .wol_irq = 63, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm440ep_mal0_def = {
- .num_tx_chans = 4, /* Number of TX channels */
- .num_rx_chans = 2, /* Number of RX channels */
- .txeob_irq = 10, /* TX End Of Buffer IRQ */
- .rxeob_irq = 11, /* RX End Of Buffer IRQ */
- .txde_irq = 33, /* TX Descriptor Error IRQ */
- .rxde_irq = 34, /* RX Descriptor Error IRQ */
- .serr_irq = 32, /* MAL System Error IRQ */
- .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm440ep_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ibm440ep_iic1_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_OPB,
- .index = 0,
- .paddr = 0x0EF600000ULL,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = PPC440EP_UART0_ADDR,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = PPC440EP_UART1_ADDR,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 2,
- .paddr = PPC440EP_UART2_ADDR,
- .irq = UART2_INT,
- .pm = IBM_CPM_UART2,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 3,
- .paddr = PPC440EP_UART3_ADDR,
- .irq = UART3_INT,
- .pm = IBM_CPM_UART3,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .index = 0,
- .paddr = 0x0EF600700ULL,
- .irq = 2,
- .pm = IBM_CPM_IIC0,
- .additions = &ibm440ep_iic0_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .index = 1,
- .paddr = 0x0EF600800ULL,
- .irq = 7,
- .pm = IBM_CPM_IIC1,
- .additions = &ibm440ep_iic1_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .index = 0,
- .paddr = 0x0EF600B00ULL,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .index = 1,
- .paddr = 0x0EF600C00ULL,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_MAL,
- .paddr = OCP_PADDR_NA,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- .additions = &ibm440ep_mal0_def,
- .show = &ocp_show_mal_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 0,
- .paddr = 0x0EF600E00ULL,
- .irq = 60,
- .pm = OCP_CPM_NA,
- .additions = &ibm440ep_emac0_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 1,
- .paddr = 0x0EF600F00ULL,
- .irq = 62,
- .pm = OCP_CPM_NA,
- .additions = &ibm440ep_emac1_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_ZMII,
- .paddr = 0x0EF600D00ULL,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_INVALID
- }
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
- { .polarity = 0xffbffe03,
- .triggering = 0x00000000,
- .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
- },
- { .polarity = 0xffffc6af,
- .triggering = 0x06000140,
- .ext_irq_mask = 0x00003800, /* IRQ7 - IRQ9 */
- },
-};
-
-static struct resource usb_gadget_resources[] = {
- [0] = {
- .start = 0x050000100ULL,
- .end = 0x05000017FULL,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 55,
- .end = 55,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 dma_mask = 0xffffffffULL;
-
-static struct platform_device usb_gadget_device = {
- .name = "musbhsfc",
- .id = 0,
- .num_resources = ARRAY_SIZE(usb_gadget_resources),
- .resource = usb_gadget_resources,
- .dev = {
- .dma_mask = &dma_mask,
- .coherent_dma_mask = 0xffffffffULL,
- }
-};
-
-static struct platform_device *ibm440ep_devs[] __initdata = {
- &usb_gadget_device,
-};
-
-static int __init
-ibm440ep_platform_add_devices(void)
-{
- return platform_add_devices(ibm440ep_devs, ARRAY_SIZE(ibm440ep_devs));
-}
-arch_initcall(ibm440ep_platform_add_devices);
-
diff --git a/arch/ppc/platforms/4xx/ibm440ep.h b/arch/ppc/platforms/4xx/ibm440ep.h
deleted file mode 100644
index d92572727d20..000000000000
--- a/arch/ppc/platforms/4xx/ibm440ep.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * PPC440EP definitions
- *
- * Wade Farnsworth <wfarnsworth@mvista.com>
- *
- * Copyright 2002 Roland Dreier
- * Copyright 2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __PPC_PLATFORMS_IBM440EP_H
-#define __PPC_PLATFORMS_IBM440EP_H
-
-#include <asm/ibm44x.h>
-
-/* UART */
-#define PPC440EP_UART0_ADDR 0x0EF600300
-#define PPC440EP_UART1_ADDR 0x0EF600400
-#define PPC440EP_UART2_ADDR 0x0EF600500
-#define PPC440EP_UART3_ADDR 0x0EF600600
-#define UART0_INT 0
-#define UART1_INT 1
-#define UART2_INT 3
-#define UART3_INT 4
-
-/* Clock and Power Management */
-#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
-#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
-#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
-#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
-#define IBM_CPM_FPU 0x04000000 /* floating point unit */
-#define IBM_CPM_CPU 0x02000000 /* processor core */
-#define IBM_CPM_DMA 0x01000000 /* DMA controller */
-#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
-#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
-#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
-#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
-#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
-#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
-#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
-#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
-#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
-#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
-#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
-#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
-#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
-#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
-#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
-#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
-#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
-#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
-#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
-#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
-#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
-
-#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
- | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
- | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
- | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
- | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
- | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
-
-
-#endif /* __PPC_PLATFORMS_IBM440EP_H */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c
deleted file mode 100644
index b67a72e5c6fe..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gp.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * PPC440GP I/O descriptions
- *
- * Matt Porter <mporter@mvista.com>
- * Copyright 2002-2004 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <platforms/4xx/ibm440gp.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ibm440gp_emac0_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 0, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 0, /* MAL rx channel number */
- .mal_tx_chan = 0, /* MAL tx channel number */
- .wol_irq = 61, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-
-static struct ocp_func_emac_data ibm440gp_emac1_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 1, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 1, /* MAL rx channel number */
- .mal_tx_chan = 2, /* MAL tx channel number */
- .wol_irq = 63, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm440gp_mal0_def = {
- .num_tx_chans = 4, /* Number of TX channels */
- .num_rx_chans = 2, /* Number of RX channels */
- .txeob_irq = 10, /* TX End Of Buffer IRQ */
- .rxeob_irq = 11, /* RX End Of Buffer IRQ */
- .txde_irq = 33, /* TX Descriptor Error IRQ */
- .rxde_irq = 34, /* RX Descriptor Error IRQ */
- .serr_irq = 32, /* MAL System Error IRQ */
- .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm440gp_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ibm440gp_iic1_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_OPB,
- .index = 0,
- .paddr = 0x0000000140000000ULL,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = PPC440GP_UART0_ADDR,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = PPC440GP_UART1_ADDR,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .index = 0,
- .paddr = 0x0000000140000400ULL,
- .irq = 2,
- .pm = IBM_CPM_IIC0,
- .additions = &ibm440gp_iic0_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .index = 1,
- .paddr = 0x0000000140000500ULL,
- .irq = 3,
- .pm = IBM_CPM_IIC1,
- .additions = &ibm440gp_iic1_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .index = 0,
- .paddr = 0x0000000140000700ULL,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_MAL,
- .paddr = OCP_PADDR_NA,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- .additions = &ibm440gp_mal0_def,
- .show = &ocp_show_mal_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 0,
- .paddr = 0x0000000140000800ULL,
- .irq = 60,
- .pm = OCP_CPM_NA,
- .additions = &ibm440gp_emac0_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 1,
- .paddr = 0x0000000140000900ULL,
- .irq = 62,
- .pm = OCP_CPM_NA,
- .additions = &ibm440gp_emac1_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_ZMII,
- .paddr = 0x0000000140000780ULL,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_INVALID
- }
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
- { .polarity = 0xfffffe03,
- .triggering = 0x01c00000,
- .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
- },
- { .polarity = 0xffffc0ff,
- .triggering = 0x00ff8000,
- .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
- },
-};
diff --git a/arch/ppc/platforms/4xx/ibm440gp.h b/arch/ppc/platforms/4xx/ibm440gp.h
deleted file mode 100644
index 391c90e1f5ea..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gp.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * PPC440GP definitions
- *
- * Roland Dreier <roland@digitalvampire.org>
- *
- * Copyright 2002 Roland Dreier
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This file contains code that was originally in the files ibm44x.h
- * and ebony.h, which were written by Matt Porter of MontaVista Software Inc.
- */
-
-#ifdef __KERNEL__
-#ifndef __PPC_PLATFORMS_IBM440GP_H
-#define __PPC_PLATFORMS_IBM440GP_H
-
-
-/* UART */
-#define PPC440GP_UART0_ADDR 0x0000000140000200ULL
-#define PPC440GP_UART1_ADDR 0x0000000140000300ULL
-#define UART0_INT 0
-#define UART1_INT 1
-
-/* Clock and Power Management */
-#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
-#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
-#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
-#define IBM_CPM_CPU 0x02000000 /* processor core */
-#define IBM_CPM_DMA 0x01000000 /* DMA controller */
-#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
-#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
-#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
-#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
-#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
-#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
-#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
-#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
-#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
-#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
-#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
-#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
-#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
-
-#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
- | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
- | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
- | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI)
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE 2
-
-#include <asm/ibm44x.h>
-#include <syslib/ibm440gp_common.h>
-
-#endif /* __PPC_PLATFORMS_IBM440GP_H */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c
deleted file mode 100644
index 685abffcb6ce..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gx.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * PPC440GX I/O descriptions
- *
- * Matt Porter <mporter@mvista.com>
- * Copyright 2002-2004 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <platforms/4xx/ibm440gx.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ibm440gx_emac0_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 0, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 0, /* MAL rx channel number */
- .mal_tx_chan = 0, /* MAL tx channel number */
- .wol_irq = 61, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-
-static struct ocp_func_emac_data ibm440gx_emac1_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 1, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 1, /* MAL rx channel number */
- .mal_tx_chan = 1, /* MAL tx channel number */
- .wol_irq = 63, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-
-static struct ocp_func_emac_data ibm440gx_emac2_def = {
- .rgmii_idx = 0, /* RGMII device index */
- .rgmii_mux = 0, /* RGMII input of this EMAC */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 2, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 2, /* MAL rx channel number */
- .mal_tx_chan = 2, /* MAL tx channel number */
- .wol_irq = 65, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = 0, /* TAH device index */
-};
-
-static struct ocp_func_emac_data ibm440gx_emac3_def = {
- .rgmii_idx = 0, /* RGMII device index */
- .rgmii_mux = 1, /* RGMII input of this EMAC */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 3, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 3, /* MAL rx channel number */
- .mal_tx_chan = 3, /* MAL tx channel number */
- .wol_irq = 67, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = 1, /* TAH device index */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm440gx_mal0_def = {
- .num_tx_chans = 4, /* Number of TX channels */
- .num_rx_chans = 4, /* Number of RX channels */
- .txeob_irq = 10, /* TX End Of Buffer IRQ */
- .rxeob_irq = 11, /* RX End Of Buffer IRQ */
- .txde_irq = 33, /* TX Descriptor Error IRQ */
- .rxde_irq = 34, /* RX Descriptor Error IRQ */
- .serr_irq = 32, /* MAL System Error IRQ */
- .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm440gx_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ibm440gx_iic1_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_OPB,
- .index = 0,
- .paddr = 0x0000000140000000ULL,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = PPC440GX_UART0_ADDR,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = PPC440GX_UART1_ADDR,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .index = 0,
- .paddr = 0x0000000140000400ULL,
- .irq = 2,
- .pm = IBM_CPM_IIC0,
- .additions = &ibm440gx_iic0_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .index = 1,
- .paddr = 0x0000000140000500ULL,
- .irq = 3,
- .pm = IBM_CPM_IIC1,
- .additions = &ibm440gx_iic1_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .index = 0,
- .paddr = 0x0000000140000700ULL,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_MAL,
- .paddr = OCP_PADDR_NA,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- .additions = &ibm440gx_mal0_def,
- .show = &ocp_show_mal_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 0,
- .paddr = 0x0000000140000800ULL,
- .irq = 60,
- .pm = OCP_CPM_NA,
- .additions = &ibm440gx_emac0_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 1,
- .paddr = 0x0000000140000900ULL,
- .irq = 62,
- .pm = OCP_CPM_NA,
- .additions = &ibm440gx_emac1_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 2,
- .paddr = 0x0000000140000C00ULL,
- .irq = 64,
- .pm = OCP_CPM_NA,
- .additions = &ibm440gx_emac2_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 3,
- .paddr = 0x0000000140000E00ULL,
- .irq = 66,
- .pm = OCP_CPM_NA,
- .additions = &ibm440gx_emac3_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_RGMII,
- .paddr = 0x0000000140000790ULL,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_ZMII,
- .paddr = 0x0000000140000780ULL,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_TAH,
- .index = 0,
- .paddr = 0x0000000140000b50ULL,
- .irq = 68,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_TAH,
- .index = 1,
- .paddr = 0x0000000140000d50ULL,
- .irq = 69,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_INVALID
- }
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
- { .polarity = 0xfffffe03,
- .triggering = 0x01c00000,
- .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
- },
- { .polarity = 0xffffc0ff,
- .triggering = 0x00ff8000,
- .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
- },
- { .polarity = 0xffff83ff,
- .triggering = 0x000f83c0,
- .ext_irq_mask = 0x00007c00, /* IRQ13 - IRQ17 */
- },
-};
diff --git a/arch/ppc/platforms/4xx/ibm440gx.h b/arch/ppc/platforms/4xx/ibm440gx.h
deleted file mode 100644
index 599c4289b9c2..000000000000
--- a/arch/ppc/platforms/4xx/ibm440gx.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * PPC440GX definitions
- *
- * Matt Porter <mporter@mvista.com>
- *
- * Copyright 2002 Roland Dreier
- * Copyright 2003 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __PPC_PLATFORMS_IBM440GX_H
-#define __PPC_PLATFORMS_IBM440GX_H
-
-
-#include <asm/ibm44x.h>
-
-/* UART */
-#define PPC440GX_UART0_ADDR 0x0000000140000200ULL
-#define PPC440GX_UART1_ADDR 0x0000000140000300ULL
-#define UART0_INT 0
-#define UART1_INT 1
-
-/* Clock and Power Management */
-#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
-#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
-#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
-#define IBM_CPM_RGMII 0x10000000 /* RGMII */
-#define IBM_CPM_TAHOE0 0x08000000 /* TAHOE 0 */
-#define IBM_CPM_TAHOE1 0x04000000 /* TAHOE 1 */
-#define IBM_CPM_CPU 0x02000000 /* processor core */
-#define IBM_CPM_DMA 0x01000000 /* DMA controller */
-#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
-#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
-#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
-#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
-#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
-#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
-#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
-#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
-#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
-#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
-#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
-#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
-#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
-#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
-#define IBM_CPM_EMAC1 0x00000010 /* EMAC 1 */
-#define IBM_CPM_EMAC2 0x00000008 /* EMAC 2 */
-#define IBM_CPM_EMAC3 0x00000004 /* EMAC 3 */
-
-#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
- | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
- | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
- | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
- | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
- | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
- | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE 2
-
-#endif /* __PPC_PLATFORMS_IBM440GX_H */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
deleted file mode 100644
index de8f7ac5623c..000000000000
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * PPC440SP I/O descriptions
- *
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2002-2005 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <platforms/4xx/ibm440sp.h>
-#include <asm/ocp.h>
-
-static struct ocp_func_emac_data ibm440sp_emac0_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = -1, /* No ZMII */
- .zmii_mux = -1, /* No ZMII */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 0, /* MAL rx channel number */
- .mal_tx_chan = 0, /* MAL tx channel number */
- .wol_irq = 61, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm440sp_mal0_def = {
- .num_tx_chans = 1, /* Number of TX channels */
- .num_rx_chans = 1, /* Number of RX channels */
- .txeob_irq = 38, /* TX End Of Buffer IRQ */
- .rxeob_irq = 39, /* RX End Of Buffer IRQ */
- .txde_irq = 34, /* TX Descriptor Error IRQ */
- .rxde_irq = 35, /* RX Descriptor Error IRQ */
- .serr_irq = 33, /* MAL System Error IRQ */
- .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm440sp_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ibm440sp_iic1_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_OPB,
- .index = 0,
- .paddr = 0x0000000140000000ULL,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = PPC440SP_UART0_ADDR,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = PPC440SP_UART1_ADDR,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 2,
- .paddr = PPC440SP_UART2_ADDR,
- .irq = UART2_INT,
- .pm = IBM_CPM_UART2,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .index = 0,
- .paddr = 0x00000001f0000400ULL,
- .irq = 2,
- .pm = IBM_CPM_IIC0,
- .additions = &ibm440sp_iic0_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .index = 1,
- .paddr = 0x00000001f0000500ULL,
- .irq = 3,
- .pm = IBM_CPM_IIC1,
- .additions = &ibm440sp_iic1_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .index = 0,
- .paddr = 0x00000001f0000700ULL,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_MAL,
- .paddr = OCP_PADDR_NA,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- .additions = &ibm440sp_mal0_def,
- .show = &ocp_show_mal_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 0,
- .paddr = 0x00000001f0000800ULL,
- .irq = 60,
- .pm = OCP_CPM_NA,
- .additions = &ibm440sp_emac0_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_INVALID
- }
-};
diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h
deleted file mode 100644
index 2978682f1720..000000000000
--- a/arch/ppc/platforms/4xx/ibm440sp.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * PPC440SP definitions
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2004-2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __PPC_PLATFORMS_IBM440SP_H
-#define __PPC_PLATFORMS_IBM440SP_H
-
-
-#include <asm/ibm44x.h>
-
-/* UART */
-#define PPC440SP_UART0_ADDR 0x00000001f0000200ULL
-#define PPC440SP_UART1_ADDR 0x00000001f0000300ULL
-#define PPC440SP_UART2_ADDR 0x00000001f0000600ULL
-#define UART0_INT 0
-#define UART1_INT 1
-#define UART2_INT 2
-
-/* Clock and Power Management */
-#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
-#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
-#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
-#define IBM_CPM_CPU 0x02000000 /* processor core */
-#define IBM_CPM_DMA 0x01000000 /* DMA controller */
-#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
-#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
-#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
-#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
-#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
-#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
-#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
-#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
-#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
-#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
-#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
-#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
-#define IBM_CPM_UART2 0x00000100 /* serial port 1 */
-#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
-#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
-
-#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
- | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
- | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
- | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
- | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
- | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
- | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
-#endif /* __PPC_PLATFORMS_IBM440SP_H */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.c b/arch/ppc/platforms/4xx/ibmnp405h.c
deleted file mode 100644
index 1afc3642e5b1..000000000000
--- a/arch/ppc/platforms/4xx/ibmnp405h.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <asm/ocp.h>
-#include <platforms/4xx/ibmnp405h.h>
-
-static struct ocp_func_emac_data ibmnp405h_emac0_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 0, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 0, /* MAL rx channel number */
- .mal_tx_chan = 0, /* MAL tx channel number */
- .wol_irq = 41, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-
-static struct ocp_func_emac_data ibmnp405h_emac1_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 1, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 1, /* MAL rx channel number */
- .mal_tx_chan = 2, /* MAL tx channel number */
- .wol_irq = 41, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-static struct ocp_func_emac_data ibmnp405h_emac2_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 2, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 2, /* MAL rx channel number */
- .mal_tx_chan = 4, /* MAL tx channel number */
- .wol_irq = 41, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-static struct ocp_func_emac_data ibmnp405h_emac3_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = 0, /* ZMII device index */
- .zmii_mux = 3, /* ZMII input of this EMAC */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 3, /* MAL rx channel number */
- .mal_tx_chan = 6, /* MAL tx channel number */
- .wol_irq = 41, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibmnp405h_mal0_def = {
- .num_tx_chans = 8, /* Number of TX channels */
- .num_rx_chans = 4, /* Number of RX channels */
- .txeob_irq = 17, /* TX End Of Buffer IRQ */
- .rxeob_irq = 18, /* RX End Of Buffer IRQ */
- .txde_irq = 46, /* TX Descriptor Error IRQ */
- .rxde_irq = 47, /* RX Descriptor Error IRQ */
- .serr_irq = 45, /* MAL System Error IRQ */
- .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibmnp405h_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_OPB,
- .index = 0,
- .paddr = 0xEF600000,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = UART0_IO_BASE,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = UART1_IO_BASE,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .paddr = 0xEF600500,
- .irq = 2,
- .pm = IBM_CPM_IIC0,
- .additions = &ibmnp405h_iic0_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .paddr = 0xEF600700,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_MAL,
- .paddr = OCP_PADDR_NA,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- .additions = &ibmnp405h_mal0_def,
- .show = &ocp_show_mal_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 0,
- .paddr = EMAC0_BASE,
- .irq = 37,
- .pm = IBM_CPM_EMAC0,
- .additions = &ibmnp405h_emac0_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 1,
- .paddr = 0xEF600900,
- .irq = 38,
- .pm = IBM_CPM_EMAC1,
- .additions = &ibmnp405h_emac1_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 2,
- .paddr = 0xEF600a00,
- .irq = 39,
- .pm = IBM_CPM_EMAC2,
- .additions = &ibmnp405h_emac2_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 3,
- .paddr = 0xEF600b00,
- .irq = 40,
- .pm = IBM_CPM_EMAC3,
- .additions = &ibmnp405h_emac3_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_ZMII,
- .paddr = 0xEF600C10,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_INVALID
- }
-};
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.h b/arch/ppc/platforms/4xx/ibmnp405h.h
deleted file mode 100644
index 08a6a7791903..000000000000
--- a/arch/ppc/platforms/4xx/ibmnp405h.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBMNP405H_H__
-#define __ASM_IBMNP405H_H__
-
-
-/* ibm405.h at bottom of this file */
-
-#define PPC405_PCI_CONFIG_ADDR 0xeec00000
-#define PPC405_PCI_CONFIG_DATA 0xeec00004
-#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
- /* setbat */
-#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
-#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
-#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
-
-#define PPC405_PCI_LOWER_MEM 0x00000000 /* hose_a->mem_space.start */
-#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
-#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
-#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
-
-#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
-
-#define PPC4xx_PCI_IO_ADDR ((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
-#define PPC4xx_PCI_CFG_ADDR ((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
-#define PPC4xx_PCI_LCFG_ADDR ((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
-#define PPC4xx_ONB_IO_ADDR ((uint)0xef600000)
-#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
-
-/* serial port defines */
-#define RS_TABLE_SIZE 4
-
-#define UART0_INT 0
-#define UART1_INT 1
-#define PCIL0_BASE 0xEF400000
-#define UART0_IO_BASE 0xEF600300
-#define UART1_IO_BASE 0xEF600400
-#define OPB0_BASE 0xEF600600
-#define EMAC0_BASE 0xEF600800
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
-
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base:(u8 *) UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1)
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(1) \
- STD_UART_OP(0)
-#endif
-
-/* DCR defines */
-/* ------------------------------------------------------------------------- */
-
-#define DCRN_CHCR_BASE 0x0F1
-#define DCRN_CHPSR_BASE 0x0B4
-#define DCRN_CPMSR_BASE 0x0BA
-#define DCRN_CPMFR_BASE 0x0B9
-#define DCRN_CPMER_BASE 0x0B8
-
-/* CPM Clocking & Power Management defines */
-#define IBM_CPM_PCI 0x40000000 /* PCI */
-#define IBM_CPM_EMAC2 0x20000000 /* EMAC 2 MII */
-#define IBM_CPM_EMAC3 0x04000000 /* EMAC 3 MII */
-#define IBM_CPM_EMAC0 0x00800000 /* EMAC 0 MII */
-#define IBM_CPM_EMAC1 0x00100000 /* EMAC 1 MII */
-#define IBM_CPM_EMMII 0 /* Shift value for MII */
-#define IBM_CPM_EMRX 1 /* Shift value for recv */
-#define IBM_CPM_EMTX 2 /* Shift value for MAC */
-#define IBM_CPM_UIC1 0x00020000 /* Universal Interrupt Controller */
-#define IBM_CPM_UIC0 0x00010000 /* Universal Interrupt Controller */
-#define IBM_CPM_CPU 0x00008000 /* processor core */
-#define IBM_CPM_EBC 0x00004000 /* ROM/SRAM peripheral controller */
-#define IBM_CPM_SDRAM0 0x00002000 /* SDRAM memory controller */
-#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO (??) */
-#define IBM_CPM_HDLC 0x00000800 /* HDCL */
-#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
-#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
-#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
-#define IBM_CPM_DMA 0x00000040 /* DMA controller */
-#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
-#define IBM_CPM_UART0 0x00000002 /* serial port 0 */
-#define IBM_CPM_UART1 0x00000001 /* serial port 1 */
-/* this is the default setting for devices put to sleep when booting */
-
-#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
- | IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
- | IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA \
- | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2 \
- | IBM_CPM_EMAC3 | IBM_CPM_PCI)
-
-#define DCRN_DMA0_BASE 0x100
-#define DCRN_DMA1_BASE 0x108
-#define DCRN_DMA2_BASE 0x110
-#define DCRN_DMA3_BASE 0x118
-#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
-#define DCRN_DMASR_BASE 0x120
-#define DCRN_EBC_BASE 0x012
-#define DCRN_DCP0_BASE 0x014
-#define DCRN_MAL_BASE 0x180
-#define DCRN_OCM0_BASE 0x018
-#define DCRN_PLB0_BASE 0x084
-#define DCRN_PLLMR_BASE 0x0B0
-#define DCRN_POB0_BASE 0x0A0
-#define DCRN_SDRAM0_BASE 0x010
-#define DCRN_UIC0_BASE 0x0C0
-#define DCRN_UIC1_BASE 0x0D0
-#define DCRN_CPC0_EPRCSR 0x0F3
-
-#define UIC0_UIC1NC 0x00000002
-
-#define CHR1_CETE 0x00000004 /* CPU external timer enable */
-#define UIC0 DCRN_UIC0_BASE
-#define UIC1 DCRN_UIC1_BASE
-
-#undef NR_UICS
-#define NR_UICS 2
-
-/* EMAC DCRN's FIXME: armin */
-#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
-#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
-#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
-#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
-#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
-#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
-#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
-#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
-
-#include <asm/ibm405.h>
-
-#endif /* __ASM_IBMNP405H_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c
deleted file mode 100644
index 799a2eccccc3..000000000000
--- a/arch/ppc/platforms/4xx/ibmstb4.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-#include <platforms/4xx/ibmstb4.h>
-
-static struct ocp_func_iic_data ibmstb4_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ibmstb4_iic1_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] __initdata = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = UART0_IO_BASE,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = UART1_IO_BASE,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 2,
- .paddr = UART2_IO_BASE,
- .irq = UART2_INT,
- .pm = IBM_CPM_UART2,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .paddr = IIC0_BASE,
- .irq = IIC0_IRQ,
- .pm = IBM_CPM_IIC0,
- .additions = &ibmstb4_iic0_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .paddr = IIC1_BASE,
- .irq = IIC1_IRQ,
- .pm = IBM_CPM_IIC1,
- .additions = &ibmstb4_iic1_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .paddr = GPIO0_BASE,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IDE,
- .paddr = IDE0_BASE,
- .irq = IDE0_IRQ,
- .pm = OCP_CPM_NA,
- },
- { .vendor = OCP_VENDOR_INVALID,
- }
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
- { .polarity = 0x7fffff01,
- .triggering = 0x00000000,
- .ext_irq_mask = 0x0000007e, /* IRQ0 - IRQ5 */
- }
-};
-
-static struct resource ohci_usb_resources[] = {
- [0] = {
- .start = USB0_BASE,
- .end = USB0_BASE + USB0_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = USB0_IRQ,
- .end = USB0_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 dma_mask = 0xffffffffULL;
-
-static struct platform_device ohci_usb_device = {
- .name = "ppc-soc-ohci",
- .id = 0,
- .num_resources = ARRAY_SIZE(ohci_usb_resources),
- .resource = ohci_usb_resources,
- .dev = {
- .dma_mask = &dma_mask,
- .coherent_dma_mask = 0xffffffffULL,
- }
-};
-
-static struct platform_device *ibmstb4_devs[] __initdata = {
- &ohci_usb_device,
-};
-
-static int __init
-ibmstb4_platform_add_devices(void)
-{
- return platform_add_devices(ibmstb4_devs, ARRAY_SIZE(ibmstb4_devs));
-}
-arch_initcall(ibmstb4_platform_add_devices);
diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h
deleted file mode 100644
index 31a08abaa4a2..000000000000
--- a/arch/ppc/platforms/4xx/ibmstb4.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBMSTB4_H__
-#define __ASM_IBMSTB4_H__
-
-
-/* serial port defines */
-#define STB04xxx_IO_BASE ((uint)0xe0000000)
-#define PPC4xx_PCI_IO_ADDR STB04xxx_IO_BASE
-#define PPC4xx_ONB_IO_PADDR STB04xxx_IO_BASE
-#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
-#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
-
-/*
- * map STB04xxx internal i/o address (0x400x00xx) to an address
- * which is below the 2GB limit...
- *
- * 4000 000x uart1 -> 0xe000 000x
- * 4001 00xx ppu
- * 4002 00xx smart card
- * 4003 000x iic
- * 4004 000x uart0
- * 4005 0xxx timer
- * 4006 00xx gpio
- * 4007 00xx smart card
- * 400b 000x iic
- * 400c 000x scp
- * 400d 000x modem
- * 400e 000x uart2
-*/
-#define STB04xxx_MAP_IO_ADDR(a) (((uint)(a)) + (STB04xxx_IO_BASE - 0x40000000))
-
-#define RS_TABLE_SIZE 3
-#define UART0_INT 20
-
-#ifdef __BOOTER__
-#define UART0_IO_BASE 0x40040000
-#else
-#define UART0_IO_BASE 0xe0040000
-#endif
-
-#define UART1_INT 21
-
-#ifdef __BOOTER__
-#define UART1_IO_BASE 0x40000000
-#else
-#define UART1_IO_BASE 0xe0000000
-#endif
-
-#define UART2_INT 31
-#ifdef __BOOTER__
-#define UART2_IO_BASE 0x400e0000
-#else
-#define UART2_IO_BASE 0xe00e0000
-#endif
-
-#define IDE0_BASE 0x400F0000
-#define IDE0_SIZE 0x200
-#define IDE0_IRQ 25
-#define IIC0_BASE 0x40030000
-#define IIC1_BASE 0x400b0000
-#define OPB0_BASE 0x40000000
-#define GPIO0_BASE 0x40060000
-
-#define USB0_BASE 0x40010000
-#define USB0_SIZE 0xA0
-#define USB0_IRQ 18
-
-#define IIC_NUMS 2
-#define UART_NUMS 3
-#define IIC0_IRQ 9
-#define IIC1_IRQ 10
-#define IIC_OWN 0x55
-#define IIC_CLOCK 50
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
-
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (u8 *)UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1) \
- STD_UART_OP(2)
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(1) \
- STD_UART_OP(0) \
- STD_UART_OP(2)
-#endif
-
-#if defined(CONFIG_UART0_TTYS2)
-#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(2) \
- STD_UART_OP(0) \
- STD_UART_OP(1)
-#endif
-
-#define DCRN_BE_BASE 0x090
-#define DCRN_DMA0_BASE 0x0C0
-#define DCRN_DMA1_BASE 0x0C8
-#define DCRN_DMA2_BASE 0x0D0
-#define DCRN_DMA3_BASE 0x0D8
-#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
-#define DCRN_DMASR_BASE 0x0E0
-#define DCRN_PLB0_BASE 0x054
-#define DCRN_PLB1_BASE 0x064
-#define DCRN_POB0_BASE 0x0B0
-#define DCRN_SCCR_BASE 0x120
-#define DCRN_UIC0_BASE 0x040
-#define DCRN_BE_BASE 0x090
-#define DCRN_DMA0_BASE 0x0C0
-#define DCRN_DMA1_BASE 0x0C8
-#define DCRN_DMA2_BASE 0x0D0
-#define DCRN_DMA3_BASE 0x0D8
-#define DCRN_CIC_BASE 0x030
-#define DCRN_DMASR_BASE 0x0E0
-#define DCRN_EBIMC_BASE 0x070
-#define DCRN_DCRX_BASE 0x020
-#define DCRN_CPMFR_BASE 0x102
-#define DCRN_SCCR_BASE 0x120
-#define UIC0 DCRN_UIC0_BASE
-
-#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
-#define IBM_CPM_USB0 0x40000000 /* IEEE-1284 */
-#define IBM_CPM_IIC1 0x20000000 /* IIC 1 interface */
-#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
-#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
-#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
-#define IBM_CPM_SDRAM1 0x02000000 /* SDRAM 1 memory controller */
-#define IBM_CPM_DMA 0x01000000 /* DMA controller */
-#define IBM_CPM_DMA1 0x00800000 /* reserved */
-#define IBM_CPM_XPT1 0x00400000 /* reserved */
-#define IBM_CPM_XPT2 0x00200000 /* reserved */
-#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
-#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
-#define IBM_CPM_EPI 0x00040000 /* DCR Extension */
-#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
-#define IBM_CPM_VID 0x00010000 /* reserved */
-#define IBM_CPM_SC1 0x00008000 /* Smart Card 1 */
-#define IBM_CPM_USBSDRA 0x00004000 /* SDRAM 0 memory controller */
-#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
-#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
-#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
-#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
-#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
-#define IBM_CPM_TMRCLK 0x00000100 /* CPU timers */
-#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
-#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
-#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
-#define IBM_CPM_UART2 0x00000008 /* Serial Control Port */
-#define IBM_CPM_DDIO 0x00000004 /* Descrambler */
-#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
-
-#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
- | IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \
- | IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \
- | IBM_CPM_XPT27 | IBM_CPM_UIC )
-
-#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
-#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
-/* DCRN_BESR */
-#define BESR_DSES 0x80000000 /* Data-Side Error Status */
-#define BESR_DMES 0x40000000 /* DMA Error Status */
-#define BESR_RWS 0x20000000 /* Read/Write Status */
-#define BESR_ETMASK 0x1C000000 /* Error Type */
-#define ET_PROT 0
-#define ET_PARITY 1
-#define ET_NCFG 2
-#define ET_BUSERR 4
-#define ET_BUSTO 6
-
-#define CHR1_CETE 0x00800000 /* CPU external timer enable */
-#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
-
-#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
-#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
-#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
-#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
-#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
-#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
-#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
-#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
-#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
-
-#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
-#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
-#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
-#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
-#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
-#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
-#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
-#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
-
-#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
-#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
-#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
-#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
-#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
-#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
-#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
-#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
-#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
-#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
-#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
-#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
-#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
-#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
-#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
-#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
-#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
-#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
-#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
-
-#include <asm/ibm405.h>
-
-#endif /* __ASM_IBMSTB4_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmstbx25.c b/arch/ppc/platforms/4xx/ibmstbx25.c
deleted file mode 100644
index 090ddcbecc5e..000000000000
--- a/arch/ppc/platforms/4xx/ibmstbx25.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <asm/ocp.h>
-#include <platforms/4xx/ibmstbx25.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_iic_data ibmstbx25_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] __initdata = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = UART0_IO_BASE,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = UART1_IO_BASE,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 2,
- .paddr = UART2_IO_BASE,
- .irq = UART2_INT,
- .pm = IBM_CPM_UART2,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .paddr = IIC0_BASE,
- .irq = IIC0_IRQ,
- .pm = IBM_CPM_IIC0,
- .additions = &ibmstbx25_iic0_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .paddr = GPIO0_BASE,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0,
- },
- { .vendor = OCP_VENDOR_INVALID
- }
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
- { .polarity = 0xffff8f80,
- .triggering = 0x00000000,
- .ext_irq_mask = 0x0000707f, /* IRQ7 - IRQ9, IRQ0 - IRQ6 */
- }
-};
diff --git a/arch/ppc/platforms/4xx/ibmstbx25.h b/arch/ppc/platforms/4xx/ibmstbx25.h
deleted file mode 100644
index 31b63343e641..000000000000
--- a/arch/ppc/platforms/4xx/ibmstbx25.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBMSTBX25_H__
-#define __ASM_IBMSTBX25_H__
-
-
-/* serial port defines */
-#define STBx25xx_IO_BASE ((uint)0xe0000000)
-#define PPC4xx_ONB_IO_PADDR STBx25xx_IO_BASE
-#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
-#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
-
-/*
- * map STBxxxx internal i/o address (0x400x00xx) to an address
- * which is below the 2GB limit...
- *
- * 4000 000x uart1 -> 0xe000 000x
- * 4001 00xx uart2
- * 4002 00xx smart card
- * 4003 000x iic
- * 4004 000x uart0
- * 4005 0xxx timer
- * 4006 00xx gpio
- * 4007 00xx smart card
- * 400b 000x iic
- * 400c 000x scp
- * 400d 000x modem
- * 400e 000x uart2
-*/
-#define STBx25xx_MAP_IO_ADDR(a) (((uint)(a)) + (STBx25xx_IO_BASE - 0x40000000))
-
-#define RS_TABLE_SIZE 3
-
-#define OPB_BASE_START 0x40000000
-#define EBIU_BASE_START 0xF0100000
-#define DCR_BASE_START 0x0000
-
-#ifdef __BOOTER__
-#define UART1_IO_BASE 0x40000000
-#define UART2_IO_BASE 0x40010000
-#else
-#define UART1_IO_BASE 0xe0000000
-#define UART2_IO_BASE 0xe0010000
-#endif
-#define SC0_BASE 0x40020000 /* smart card #0 */
-#define IIC0_BASE 0x40030000
-#ifdef __BOOTER__
-#define UART0_IO_BASE 0x40040000
-#else
-#define UART0_IO_BASE 0xe0040000
-#endif
-#define SCC0_BASE 0x40040000 /* Serial 0 controller IrdA */
-#define GPT0_BASE 0x40050000 /* General purpose timers */
-#define GPIO0_BASE 0x40060000
-#define SC1_BASE 0x40070000 /* smart card #1 */
-#define SCP0_BASE 0x400C0000 /* Serial Controller Port */
-#define SSP0_BASE 0x400D0000 /* Sync serial port */
-
-#define IDE0_BASE 0xf0100000
-#define REDWOOD_IDE_CTRL 0xf1100000
-
-#define RTCFPC_IRQ 0
-#define XPORT_IRQ 1
-#define AUD_IRQ 2
-#define AID_IRQ 3
-#define DMA0 4
-#define DMA1_IRQ 5
-#define DMA2_IRQ 6
-#define DMA3_IRQ 7
-#define SC0_IRQ 8
-#define IIC0_IRQ 9
-#define IIR0_IRQ 10
-#define GPT0_IRQ 11
-#define GPT1_IRQ 12
-#define SCP0_IRQ 13
-#define SSP0_IRQ 14
-#define GPT2_IRQ 15 /* count down timer */
-#define SC1_IRQ 16
-/* IRQ 17 - 19 external */
-#define UART0_INT 20
-#define UART1_INT 21
-#define UART2_INT 22
-#define XPTDMA_IRQ 23
-#define DCRIDE_IRQ 24
-/* IRQ 25 - 30 external */
-#define IDE0_IRQ 26
-
-#define IIC_NUMS 1
-#define UART_NUMS 3
-#define IIC_OWN 0x55
-#define IIC_CLOCK 50
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
-
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (u8 *)UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1) \
- STD_UART_OP(2)
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(1) \
- STD_UART_OP(0) \
- STD_UART_OP(2)
-#endif
-
-#if defined(CONFIG_UART0_TTYS2)
-#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(2) \
- STD_UART_OP(0) \
- STD_UART_OP(1)
-#endif
-
-#define DCRN_BE_BASE 0x090
-#define DCRN_DMA0_BASE 0x0C0
-#define DCRN_DMA1_BASE 0x0C8
-#define DCRN_DMA2_BASE 0x0D0
-#define DCRN_DMA3_BASE 0x0D8
-#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
-#define DCRN_DMASR_BASE 0x0E0
-#define DCRN_PLB0_BASE 0x054
-#define DCRN_PLB1_BASE 0x064
-#define DCRN_POB0_BASE 0x0B0
-#define DCRN_SCCR_BASE 0x120
-#define DCRN_UIC0_BASE 0x040
-#define DCRN_BE_BASE 0x090
-#define DCRN_DMA0_BASE 0x0C0
-#define DCRN_DMA1_BASE 0x0C8
-#define DCRN_DMA2_BASE 0x0D0
-#define DCRN_DMA3_BASE 0x0D8
-#define DCRN_CIC_BASE 0x030
-#define DCRN_DMASR_BASE 0x0E0
-#define DCRN_EBIMC_BASE 0x070
-#define DCRN_DCRX_BASE 0x020
-#define DCRN_CPMFR_BASE 0x102
-#define DCRN_SCCR_BASE 0x120
-#define DCRN_RTCFP_BASE 0x310
-
-#define UIC0 DCRN_UIC0_BASE
-
-#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
-#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
-#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
-#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
-#define IBM_CPM_IRR 0x02000000 /* Infrared receiver */
-#define IBM_CPM_DMA 0x01000000 /* DMA controller */
-#define IBM_CPM_UART2 0x00200000 /* Serial Control Port */
-#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
-#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
-#define IBM_PM_DCRIDE 0x00040000 /* DCR timeout & IDE line Mode clock */
-#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
-#define IBM_CPM_VID 0x00010000 /* reserved */
-#define IBM_CPM_SC1 0x00008000 /* Smart Card 0 */
-#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
-#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
-#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
-#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
-#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
-#define IBM_CPM_C405T 0x00000100 /* CPU timers */
-#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
-#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
-#define IBM_CPM_RTCFPC 0x00000020 /* Realtime clock and front panel */
-#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
-#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
-#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_DMA \
- | IBM_CPM_CBS | IBM_CPM_XPT0 | IBM_CPM_C405T \
- | IBM_CPM_XPT27 | IBM_CPM_UIC)
-
-#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
-#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
-/* DCRN_BESR */
-#define BESR_DSES 0x80000000 /* Data-Side Error Status */
-#define BESR_DMES 0x40000000 /* DMA Error Status */
-#define BESR_RWS 0x20000000 /* Read/Write Status */
-#define BESR_ETMASK 0x1C000000 /* Error Type */
-#define ET_PROT 0
-#define ET_PARITY 1
-#define ET_NCFG 2
-#define ET_BUSERR 4
-#define ET_BUSTO 6
-
-#define CHR1_CETE 0x00800000 /* CPU external timer enable */
-#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
-
-#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
-#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
-#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
-#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
-#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
-#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
-#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
-#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
-#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
-
-#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
-#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
-#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
-#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
-#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
-#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
-#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
-#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
-
-#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
-#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
-#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
-#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
-#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
-#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
-#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
-#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
-#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
-#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
-#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
-#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
-#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
-#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
-#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
-#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
-#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
-#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
-#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
-
-#define DCRN_RTC_FPC0_CNTL (DCRN_RTCFP_BASE + 0x00) /* RTC cntl */
-#define DCRN_RTC_FPC0_INT (DCRN_RTCFP_BASE + 0x01) /* RTC Interrupt */
-#define DCRN_RTC_FPC0_TIME (DCRN_RTCFP_BASE + 0x02) /* RTC time reg */
-#define DCRN_RTC_FPC0_ALRM (DCRN_RTCFP_BASE + 0x03) /* RTC Alarm reg */
-#define DCRN_RTC_FPC0_D1 (DCRN_RTCFP_BASE + 0x04) /* LED Data 1 */
-#define DCRN_RTC_FPC0_D2 (DCRN_RTCFP_BASE + 0x05) /* LED Data 2 */
-#define DCRN_RTC_FPC0_D3 (DCRN_RTCFP_BASE + 0x06) /* LED Data 3 */
-#define DCRN_RTC_FPC0_D4 (DCRN_RTCFP_BASE + 0x07) /* LED Data 4 */
-#define DCRN_RTC_FPC0_D5 (DCRN_RTCFP_BASE + 0x08) /* LED Data 5 */
-#define DCRN_RTC_FPC0_FCNTL (DCRN_RTCFP_BASE + 0x09) /* LED control */
-#define DCRN_RTC_FPC0_BRT (DCRN_RTCFP_BASE + 0x0A) /* Brightness cntl */
-
-#include <asm/ibm405.h>
-
-#endif /* __ASM_IBMSTBX25_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c
deleted file mode 100644
index f6d8c2e8b6b7..000000000000
--- a/arch/ppc/platforms/4xx/luan.c
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
- * Luan board specific routines
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2004-2005 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/pci-bridge.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/ppcboot.h>
-
-#include <syslib/ibm44x_common.h>
-#include <syslib/ibm440gx_common.h>
-#include <syslib/ibm440sp_common.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-static void __init
-luan_calibrate_decr(void)
-{
- unsigned int freq;
-
- if (mfspr(SPRN_CCR1) & CCR1_TCS)
- freq = LUAN_TMR_CLK;
- else
- freq = clocks.cpu;
-
- ibm44x_calibrate_decr(freq);
-}
-
-static int
-luan_show_cpuinfo(struct seq_file *m)
-{
- seq_printf(m, "vendor\t\t: IBM\n");
- seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n");
-
- return 0;
-}
-
-static inline int
-luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
-
- /* PCIX0 in adapter mode, no host interrupt routing */
-
- /* PCIX1 */
- if (hose->index == 0) {
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 49, 49, 49, 49 }, /* IDSEL 1 - PCIX1 Slot 0 */
- { 49, 49, 49, 49 }, /* IDSEL 2 - PCIX1 Slot 1 */
- { 49, 49, 49, 49 }, /* IDSEL 3 - PCIX1 Slot 2 */
- { 49, 49, 49, 49 }, /* IDSEL 4 - PCIX1 Slot 3 */
- };
- const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
- /* PCIX2 */
- } else if (hose->index == 1) {
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 50, 50, 50, 50 }, /* IDSEL 1 - PCIX2 Slot 0 */
- { 50, 50, 50, 50 }, /* IDSEL 2 - PCIX2 Slot 1 */
- { 50, 50, 50, 50 }, /* IDSEL 3 - PCIX2 Slot 2 */
- { 50, 50, 50, 50 }, /* IDSEL 4 - PCIX2 Slot 3 */
- };
- const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
- }
- return -1;
-}
-
-static void __init luan_set_emacdata(void)
-{
- struct ocp_def *def;
- struct ocp_func_emac_data *emacdata;
-
- /* Set phy_map, phy_mode, and mac_addr for the EMAC */
- def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
- emacdata = def->additions;
- emacdata->phy_map = 0x00000001; /* Skip 0x00 */
- emacdata->phy_mode = PHY_MODE_GMII;
- memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
-}
-
-#define PCIX_READW(offset) \
- (readw((void *)((u32)pcix_reg_base+offset)))
-
-#define PCIX_WRITEW(value, offset) \
- (writew(value, (void *)((u32)pcix_reg_base+offset)))
-
-#define PCIX_WRITEL(value, offset) \
- (writel(value, (void *)((u32)pcix_reg_base+offset)))
-
-static void __init
-luan_setup_pcix(void)
-{
- int i;
- void *pcix_reg_base;
-
- for (i=0;i<3;i++) {
- pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE);
-
- /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
- PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
-
- /* Disable all windows */
- PCIX_WRITEL(0, PCIX0_POM0SA);
- PCIX_WRITEL(0, PCIX0_POM1SA);
- PCIX_WRITEL(0, PCIX0_POM2SA);
- PCIX_WRITEL(0, PCIX0_PIM0SA);
- PCIX_WRITEL(0, PCIX0_PIM0SAH);
- PCIX_WRITEL(0, PCIX0_PIM1SA);
- PCIX_WRITEL(0, PCIX0_PIM2SA);
- PCIX_WRITEL(0, PCIX0_PIM2SAH);
-
- /*
- * Setup 512MB PLB->PCI outbound mem window
- * (a_n000_0000->0_n000_0000)
- * */
- PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
- PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
- PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
- PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
- PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
-
- /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
- PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
- PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
- PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
- PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
-
- iounmap(pcix_reg_base);
- }
-
- eieio();
-}
-
-static void __init
-luan_setup_hose(struct pci_controller *hose,
- int lower_mem,
- int upper_mem,
- int cfga,
- int cfgd,
- u64 pcix_io_base)
-{
- char name[20];
-
- sprintf(name, "PCIX%d host bridge", hose->index);
-
- hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
-
- pci_init_resource(&hose->io_resource,
- LUAN_PCIX_LOWER_IO,
- LUAN_PCIX_UPPER_IO,
- IORESOURCE_IO,
- name);
-
- pci_init_resource(&hose->mem_resources[0],
- lower_mem,
- upper_mem,
- IORESOURCE_MEM,
- name);
-
- hose->io_space.start = LUAN_PCIX_LOWER_IO;
- hose->io_space.end = LUAN_PCIX_UPPER_IO;
- hose->mem_space.start = lower_mem;
- hose->mem_space.end = upper_mem;
- hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE);
- isa_io_base = (unsigned long) hose->io_base_virt;
-
- setup_indirect_pci(hose, cfga, cfgd);
- hose->set_cfg_type = 1;
-}
-
-static void __init
-luan_setup_hoses(void)
-{
- struct pci_controller *hose1, *hose2;
-
- /* Configure windows on the PCI-X host bridge */
- luan_setup_pcix();
-
- /* Allocate hoses for PCIX1 and PCIX2 */
- hose1 = pcibios_alloc_controller();
- if (!hose1)
- return;
-
- hose2 = pcibios_alloc_controller();
- if (!hose2) {
- pcibios_free_controller(hose1);
- return;
- }
-
- /* Setup PCIX1 */
- hose1->first_busno = 0;
- hose1->last_busno = 0xff;
-
- luan_setup_hose(hose1,
- LUAN_PCIX1_LOWER_MEM,
- LUAN_PCIX1_UPPER_MEM,
- PCIX1_CFGA,
- PCIX1_CFGD,
- PCIX1_IO_BASE);
-
- hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
-
- /* Setup PCIX2 */
- hose2->first_busno = hose1->last_busno + 1;
- hose2->last_busno = 0xff;
-
- luan_setup_hose(hose2,
- LUAN_PCIX2_LOWER_MEM,
- LUAN_PCIX2_UPPER_MEM,
- PCIX2_CFGA,
- PCIX2_CFGD,
- PCIX2_IO_BASE);
-
- hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
-
- ppc_md.pci_swizzle = common_swizzle;
- ppc_md.pci_map_irq = luan_map_irq;
-}
-
-TODC_ALLOC();
-
-static void __init
-luan_early_serial_map(void)
-{
- struct uart_port port;
-
- /* Setup ioremapped serial port access */
- memset(&port, 0, sizeof(port));
- port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
- port.irq = UART0_INT;
- port.uartclk = clocks.uart0;
- port.regshift = 0;
- port.iotype = UPIO_MEM;
- port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- port.line = 0;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 0 failed\n");
- }
-
- port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
- port.irq = UART1_INT;
- port.uartclk = clocks.uart1;
- port.line = 1;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 1 failed\n");
- }
-
- port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
- port.irq = UART2_INT;
- port.uartclk = BASE_BAUD;
- port.line = 2;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 2 failed\n");
- }
-}
-
-static void __init
-luan_setup_arch(void)
-{
- luan_set_emacdata();
-
-#if !defined(CONFIG_BDI_SWITCH)
- /*
- * The Abatron BDI JTAG debugger does not tolerate others
- * mucking with the debug registers.
- */
- mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
-#endif
-
- /*
- * Determine various clocks.
- * To be completely correct we should get SysClk
- * from FPGA, because it can be changed by on-board switches
- * --ebs
- */
- /* 440GX and 440SP clocking is the same -mdp */
- ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
- ocp_sys_info.opb_bus_freq = clocks.opb;
-
- /* init to some ~sane value until calibrate_delay() runs */
- loops_per_jiffy = 50000000/HZ;
-
- /* Setup PCIXn host bridges */
- luan_setup_hoses();
-
-#ifdef CONFIG_BLK_DEV_INITRD
- if (initrd_start)
- ROOT_DEV = Root_RAM0;
- else
-#endif
-#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
-#else
- ROOT_DEV = Root_HDA1;
-#endif
-
- luan_early_serial_map();
-
- /* Identify the system */
- printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n");
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
- unsigned long r5, unsigned long r6, unsigned long r7)
-{
- ibm44x_platform_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = luan_setup_arch;
- ppc_md.show_cpuinfo = luan_show_cpuinfo;
- ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
- ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
-
- ppc_md.calibrate_decr = luan_calibrate_decr;
-#ifdef CONFIG_KGDB
- ppc_md.early_serial_map = luan_early_serial_map;
-#endif
-}
diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h
deleted file mode 100644
index 68dd46b0a5c4..000000000000
--- a/arch/ppc/platforms/4xx/luan.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Luan board definitions
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2004-2005 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_LUAN_H__
-#define __ASM_LUAN_H__
-
-#include <platforms/4xx/ibm440sp.h>
-
-/* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0 0xa0000800
-
-/* Location of MAC addresses in PIBS image */
-#define PIBS_FLASH_BASE 0xffe00000
-#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400)
-
-/* External timer clock frequency */
-#define LUAN_TMR_CLK 25000000
-
-/* Flash */
-#define LUAN_FPGA_REG_0 0x0000000148300000ULL
-#define LUAN_BOOT_LARGE_FLASH(x) (x & 0x40)
-#define LUAN_SMALL_FLASH_LOW 0x00000001ff900000ULL
-#define LUAN_SMALL_FLASH_HIGH 0x00000001ffe00000ULL
-#define LUAN_SMALL_FLASH_SIZE 0x100000
-#define LUAN_LARGE_FLASH_LOW 0x00000001ff800000ULL
-#define LUAN_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
-#define LUAN_LARGE_FLASH_SIZE 0x400000
-
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE 3
-
-/* PIBS defined UART mappings, used before early_serial_setup */
-#define UART0_IO_BASE 0xa0000200
-#define UART1_IO_BASE 0xa0000300
-#define UART2_IO_BASE 0xa0000600
-
-#define BASE_BAUD 11059200
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (void*)UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1) \
- STD_UART_OP(2)
-
-/* PCI support */
-#define LUAN_PCIX_LOWER_IO 0x00000000
-#define LUAN_PCIX_UPPER_IO 0x0000ffff
-#define LUAN_PCIX0_LOWER_MEM 0x80000000
-#define LUAN_PCIX0_UPPER_MEM 0x9fffffff
-#define LUAN_PCIX1_LOWER_MEM 0xa0000000
-#define LUAN_PCIX1_UPPER_MEM 0xbfffffff
-#define LUAN_PCIX2_LOWER_MEM 0xc0000000
-#define LUAN_PCIX2_UPPER_MEM 0xdfffffff
-
-#define LUAN_PCIX_MEM_SIZE 0x20000000
-#define LUAN_PCIX_MEM_OFFSET 0x00000000
-
-#endif /* __ASM_LUAN_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
deleted file mode 100644
index 308386ef6f77..000000000000
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * Ocotea board specific routines
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2003-2005 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/pci-bridge.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/ppcboot.h>
-#include <asm/tlbflush.h>
-
-#include <syslib/gen550.h>
-#include <syslib/ibm440gx_common.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-static void __init
-ocotea_calibrate_decr(void)
-{
- unsigned int freq;
-
- if (mfspr(SPRN_CCR1) & CCR1_TCS)
- freq = OCOTEA_TMR_CLK;
- else
- freq = clocks.cpu;
-
- ibm44x_calibrate_decr(freq);
-}
-
-static int
-ocotea_show_cpuinfo(struct seq_file *m)
-{
- seq_printf(m, "vendor\t\t: IBM\n");
- seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
- ibm440gx_show_cpuinfo(m);
- return 0;
-}
-
-static inline int
-ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
- { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
- { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
- { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
- };
-
- const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static void __init ocotea_set_emacdata(void)
-{
- struct ocp_def *def;
- struct ocp_func_emac_data *emacdata;
- int i;
-
- /*
- * Note: Current rev. board only operates in Group 4a
- * mode, so we always set EMAC0-1 for SMII and EMAC2-3
- * for RGMII (though these could run in RTBI just the same).
- *
- * The FPGA reg 3 information isn't even suitable for
- * determining the phy_mode, so if the board becomes
- * usable in !4a, it will be necessary to parse an environment
- * variable from the firmware or similar to properly configure
- * the phy_map/phy_mode.
- */
- /* Set phy_map, phy_mode, and mac_addr for each EMAC */
- for (i=0; i<4; i++) {
- def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
- emacdata = def->additions;
- if (i < 2) {
- emacdata->phy_map = 0x00000001; /* Skip 0x00 */
- emacdata->phy_mode = PHY_MODE_SMII;
- }
- else {
- emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
- emacdata->phy_mode = PHY_MODE_RGMII;
- }
- if (i == 0)
- memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
- else if (i == 1)
- memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
- else if (i == 2)
- memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
- else if (i == 3)
- memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
- }
-}
-
-#define PCIX_READW(offset) \
- (readw(pcix_reg_base+offset))
-
-#define PCIX_WRITEW(value, offset) \
- (writew(value, pcix_reg_base+offset))
-
-#define PCIX_WRITEL(value, offset) \
- (writel(value, pcix_reg_base+offset))
-
-/*
- * FIXME: This is only here to "make it work". This will move
- * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
- * configuration library. -Matt
- */
-static void __init
-ocotea_setup_pcix(void)
-{
- void *pcix_reg_base;
-
- pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
-
- /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
- PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
-
- /* Disable all windows */
- PCIX_WRITEL(0, PCIX0_POM0SA);
- PCIX_WRITEL(0, PCIX0_POM1SA);
- PCIX_WRITEL(0, PCIX0_POM2SA);
- PCIX_WRITEL(0, PCIX0_PIM0SA);
- PCIX_WRITEL(0, PCIX0_PIM0SAH);
- PCIX_WRITEL(0, PCIX0_PIM1SA);
- PCIX_WRITEL(0, PCIX0_PIM2SA);
- PCIX_WRITEL(0, PCIX0_PIM2SAH);
-
- /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
- PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
- PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
- PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
- PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
- PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
-
- /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
- PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
- PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
- PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
-
- eieio();
-}
-
-static void __init
-ocotea_setup_hose(void)
-{
- struct pci_controller *hose;
-
- /* Configure windows on the PCI-X host bridge */
- ocotea_setup_pcix();
-
- hose = pcibios_alloc_controller();
-
- if (!hose)
- return;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
-
- pci_init_resource(&hose->io_resource,
- OCOTEA_PCI_LOWER_IO,
- OCOTEA_PCI_UPPER_IO,
- IORESOURCE_IO,
- "PCI host bridge");
-
- pci_init_resource(&hose->mem_resources[0],
- OCOTEA_PCI_LOWER_MEM,
- OCOTEA_PCI_UPPER_MEM,
- IORESOURCE_MEM,
- "PCI host bridge");
-
- hose->io_space.start = OCOTEA_PCI_LOWER_IO;
- hose->io_space.end = OCOTEA_PCI_UPPER_IO;
- hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
- hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
- hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
- isa_io_base = (unsigned long) hose->io_base_virt;
-
- setup_indirect_pci(hose,
- OCOTEA_PCI_CFGA_PLB32,
- OCOTEA_PCI_CFGD_PLB32);
- hose->set_cfg_type = 1;
-
- hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
- ppc_md.pci_swizzle = common_swizzle;
- ppc_md.pci_map_irq = ocotea_map_irq;
-}
-
-
-TODC_ALLOC();
-
-static void __init
-ocotea_early_serial_map(void)
-{
- struct uart_port port;
-
- /* Setup ioremapped serial port access */
- memset(&port, 0, sizeof(port));
- port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
- port.irq = UART0_INT;
- port.uartclk = clocks.uart0;
- port.regshift = 0;
- port.iotype = UPIO_MEM;
- port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- port.line = 0;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 0 failed\n");
- }
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- /* Configure debug serial access */
- gen550_init(0, &port);
-
- /* Purge TLB entry added in head_44x.S for early serial access */
- _tlbie(UART0_IO_BASE, 0);
-#endif
-
- port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
- port.irq = UART1_INT;
- port.uartclk = clocks.uart1;
- port.line = 1;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 1 failed\n");
- }
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- /* Configure debug serial access */
- gen550_init(1, &port);
-#endif
-}
-
-static void __init
-ocotea_setup_arch(void)
-{
- ocotea_set_emacdata();
-
- ibm440gx_tah_enable();
-
- /*
- * Determine various clocks.
- * To be completely correct we should get SysClk
- * from FPGA, because it can be changed by on-board switches
- * --ebs
- */
- ibm440gx_get_clocks(&clocks, 33300000, 6 * 1843200);
- ocp_sys_info.opb_bus_freq = clocks.opb;
-
- /* Setup TODC access */
- TODC_INIT(TODC_TYPE_DS1743,
- 0,
- 0,
- ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
- 8);
-
- /* init to some ~sane value until calibrate_delay() runs */
- loops_per_jiffy = 50000000/HZ;
-
- /* Setup PCI host bridge */
- ocotea_setup_hose();
-
-#ifdef CONFIG_BLK_DEV_INITRD
- if (initrd_start)
- ROOT_DEV = Root_RAM0;
- else
-#endif
-#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
-#else
- ROOT_DEV = Root_HDA1;
-#endif
-
- ocotea_early_serial_map();
-
- /* Identify the system */
- printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
-}
-
-static void __init ocotea_init(void)
-{
- ibm440gx_l2c_setup(&clocks);
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
- unsigned long r5, unsigned long r6, unsigned long r7)
-{
- ibm440gx_platform_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = ocotea_setup_arch;
- ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
- ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
-
- ppc_md.calibrate_decr = ocotea_calibrate_decr;
- ppc_md.time_init = todc_time_init;
- ppc_md.set_rtc_time = todc_set_rtc_time;
- ppc_md.get_rtc_time = todc_get_rtc_time;
-
- ppc_md.nvram_read_val = todc_direct_read_val;
- ppc_md.nvram_write_val = todc_direct_write_val;
-#ifdef CONFIG_KGDB
- ppc_md.early_serial_map = ocotea_early_serial_map;
-#endif
- ppc_md.init = ocotea_init;
-}
diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
deleted file mode 100644
index 89730ce2322c..000000000000
--- a/arch/ppc/platforms/4xx/ocotea.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Ocotea board definitions
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2003-2005 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_OCOTEA_H__
-#define __ASM_OCOTEA_H__
-
-#include <platforms/4xx/ibm440gx.h>
-
-/* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0 0xe0000800
-
-/* Location of MAC addresses in PIBS image */
-#define PIBS_FLASH_BASE 0xfff00000
-#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xb0500)
-#define PIBS_MAC_SIZE 0x200
-#define PIBS_MAC_OFFSET 0x100
-
-/* External timer clock frequency */
-#define OCOTEA_TMR_CLK 25000000
-
-/* RTC/NVRAM location */
-#define OCOTEA_RTC_ADDR 0x0000000148000000ULL
-#define OCOTEA_RTC_SIZE 0x2000
-
-/* Flash */
-#define OCOTEA_FPGA_REG_0 0x0000000148300000ULL
-#define OCOTEA_BOOT_LARGE_FLASH(x) (x & 0x40)
-#define OCOTEA_SMALL_FLASH_LOW 0x00000001ff900000ULL
-#define OCOTEA_SMALL_FLASH_HIGH 0x00000001fff00000ULL
-#define OCOTEA_SMALL_FLASH_SIZE 0x100000
-#define OCOTEA_LARGE_FLASH_LOW 0x00000001ff800000ULL
-#define OCOTEA_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
-#define OCOTEA_LARGE_FLASH_SIZE 0x400000
-
-/* FPGA_REG_3 (Ethernet Groups) */
-#define OCOTEA_FPGA_REG_3 0x0000000148300003ULL
-
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE 2
-
-#if defined(__BOOTER__)
-/* OpenBIOS defined UART mappings, used by bootloader shim */
-#define UART0_IO_BASE 0xE0000200
-#define UART1_IO_BASE 0xE0000300
-#else
-/* head_44x.S created UART mapping, used before early_serial_setup.
- * We cannot use default OpenBIOS UART mappings because they
- * don't work for configurations with more than 512M RAM. --ebs
- */
-#define UART0_IO_BASE 0xF0000200
-#define UART1_IO_BASE 0xF0000300
-#endif
-
-#define BASE_BAUD 11059200/16
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (void*)UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1)
-
-/* PCI support */
-#define OCOTEA_PCI_LOWER_IO 0x00000000
-#define OCOTEA_PCI_UPPER_IO 0x0000ffff
-#define OCOTEA_PCI_LOWER_MEM 0x80000000
-#define OCOTEA_PCI_UPPER_MEM 0xffffefff
-
-#define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL
-#define OCOTEA_PCI_CFGA_PLB32 0x0ec00000
-#define OCOTEA_PCI_CFGD_PLB32 0x0ec00004
-
-#define OCOTEA_PCI_IO_BASE 0x0000000208000000ULL
-#define OCOTEA_PCI_IO_SIZE 0x00010000
-#define OCOTEA_PCI_MEM_OFFSET 0x00000000
-
-#endif /* __ASM_OCOTEA_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c
deleted file mode 100644
index 1be5d1c8e266..000000000000
--- a/arch/ppc/platforms/4xx/ppc440spe.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * PPC440SPe I/O descriptions
- *
- * Roland Dreier <rolandd@cisco.com>
- * Copyright (c) 2005 Cisco Systems. All rights reserved.
- *
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2002-2005 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <platforms/4xx/ppc440spe.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ppc440spe_emac0_def = {
- .rgmii_idx = -1, /* No RGMII */
- .rgmii_mux = -1, /* No RGMII */
- .zmii_idx = -1, /* No ZMII */
- .zmii_mux = -1, /* No ZMII */
- .mal_idx = 0, /* MAL device index */
- .mal_rx_chan = 0, /* MAL rx channel number */
- .mal_tx_chan = 0, /* MAL tx channel number */
- .wol_irq = 61, /* WOL interrupt number */
- .mdio_idx = -1, /* No shared MDIO */
- .tah_idx = -1, /* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ppc440spe_mal0_def = {
- .num_tx_chans = 1, /* Number of TX channels */
- .num_rx_chans = 1, /* Number of RX channels */
- .txeob_irq = 38, /* TX End Of Buffer IRQ */
- .rxeob_irq = 39, /* RX End Of Buffer IRQ */
- .txde_irq = 34, /* TX Descriptor Error IRQ */
- .rxde_irq = 35, /* RX Descriptor Error IRQ */
- .serr_irq = 33, /* MAL System Error IRQ */
- .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ppc440spe_iic0_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ppc440spe_iic1_def = {
- .fast_mode = 0, /* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 0,
- .paddr = PPC440SPE_UART0_ADDR,
- .irq = UART0_INT,
- .pm = IBM_CPM_UART0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 1,
- .paddr = PPC440SPE_UART1_ADDR,
- .irq = UART1_INT,
- .pm = IBM_CPM_UART1,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_16550,
- .index = 2,
- .paddr = PPC440SPE_UART2_ADDR,
- .irq = UART2_INT,
- .pm = IBM_CPM_UART2,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .index = 0,
- .paddr = 0x00000004f0000400ULL,
- .irq = 2,
- .pm = IBM_CPM_IIC0,
- .additions = &ppc440spe_iic0_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_IIC,
- .index = 1,
- .paddr = 0x00000004f0000500ULL,
- .irq = 3,
- .pm = IBM_CPM_IIC1,
- .additions = &ppc440spe_iic1_def,
- .show = &ocp_show_iic_data
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_GPIO,
- .index = 0,
- .paddr = 0x00000004f0000700ULL,
- .irq = OCP_IRQ_NA,
- .pm = IBM_CPM_GPIO0,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_MAL,
- .paddr = OCP_PADDR_NA,
- .irq = OCP_IRQ_NA,
- .pm = OCP_CPM_NA,
- .additions = &ppc440spe_mal0_def,
- .show = &ocp_show_mal_data,
- },
- { .vendor = OCP_VENDOR_IBM,
- .function = OCP_FUNC_EMAC,
- .index = 0,
- .paddr = 0x00000004f0000800ULL,
- .irq = 60,
- .pm = OCP_CPM_NA,
- .additions = &ppc440spe_emac0_def,
- .show = &ocp_show_emac_data,
- },
- { .vendor = OCP_VENDOR_INVALID
- }
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
- { .polarity = 0xffffffff,
- .triggering = 0x010f0004,
- .ext_irq_mask = 0x00000000,
- },
- { .polarity = 0xffffffff,
- .triggering = 0x001f8040,
- .ext_irq_mask = 0x00007c30, /* IRQ6 - IRQ7, IRQ8 - IRQ12 */
- },
- { .polarity = 0xffffffff,
- .triggering = 0x00000000,
- .ext_irq_mask = 0x000000fc, /* IRQ0 - IRQ5 */
- },
- { .polarity = 0xffffffff,
- .triggering = 0x00000000,
- .ext_irq_mask = 0x00000000,
- },
-};
diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h
deleted file mode 100644
index f1e867c4c9fc..000000000000
--- a/arch/ppc/platforms/4xx/ppc440spe.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * PPC440SPe definitions
- *
- * Roland Dreier <rolandd@cisco.com>
- * Copyright (c) 2005 Cisco Systems. All rights reserved.
- *
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2004-2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __PPC_PLATFORMS_PPC440SPE_H
-#define __PPC_PLATFORMS_PPC440SPE_H
-
-
-#include <asm/ibm44x.h>
-
-/* UART */
-#define PPC440SPE_UART0_ADDR 0x00000004f0000200ULL
-#define PPC440SPE_UART1_ADDR 0x00000004f0000300ULL
-#define PPC440SPE_UART2_ADDR 0x00000004f0000600ULL
-#define UART0_INT 0
-#define UART1_INT 1
-#define UART2_INT 37
-
-/* Clock and Power Management */
-#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
-#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
-#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
-#define IBM_CPM_CPU 0x02000000 /* processor core */
-#define IBM_CPM_DMA 0x01000000 /* DMA controller */
-#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
-#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
-#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
-#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
-#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
-#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
-#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
-#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
-#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
-#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
-#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
-#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
-#define IBM_CPM_UART2 0x00000100 /* serial port 1 */
-#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
-#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
-
-#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
- | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
- | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
- | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
- | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
- | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
- | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
-#endif /* __PPC_PLATFORMS_PPC440SP_H */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c
deleted file mode 100644
index edf4d37d1a52..000000000000
--- a/arch/ppc/platforms/4xx/redwood5.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Support for the IBM redwood5 eval board file
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/pagemap.h>
-#include <linux/platform_device.h>
-#include <linux/ioport.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ppc4xx_pic.h>
-
-/*
- * Define external IRQ senses and polarities.
- */
-unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = SMC91111_BASE_ADDR,
- .end = SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = SMC91111_IRQ,
- .end = SMC91111_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-static struct platform_device *redwood5_devs[] __initdata = {
- &smc91x_device,
-};
-
-static int __init
-redwood5_platform_add_devices(void)
-{
- return platform_add_devices(redwood5_devs, ARRAY_SIZE(redwood5_devs));
-}
-
-void __init
-redwood5_setup_arch(void)
-{
- ppc4xx_setup_arch();
-
-#ifdef CONFIG_DEBUG_BRINGUP
- printk("\n");
- printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
- printk("\n");
- printk("bi_s_version\t %s\n", bip->bi_s_version);
- printk("bi_r_version\t %s\n", bip->bi_r_version);
- printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,bip->bi_memsize/(1024*1000));
- printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
- bip->bi_enetaddr[0], bip->bi_enetaddr[1],
- bip->bi_enetaddr[2], bip->bi_enetaddr[3],
- bip->bi_enetaddr[4], bip->bi_enetaddr[5]);
-
- printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
- bip->bi_intfreq, bip->bi_intfreq/ 1000000);
-
- printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
- bip->bi_busfreq, bip->bi_busfreq / 1000000 );
- printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n",
- bip->bi_tbfreq, bip->bi_tbfreq/1000000);
-
- printk("\n");
-#endif
- device_initcall(redwood5_platform_add_devices);
-}
-
-void __init
-redwood5_map_io(void)
-{
- int i;
-
- ppc4xx_map_io();
- for (i = 0; i < 16; i++) {
- unsigned long v, p;
-
- /* 0x400x0000 -> 0xe00x0000 */
- p = 0x40000000 | (i << 16);
- v = STB04xxx_IO_BASE | (i << 16);
-
- io_block_mapping(v, p, PAGE_SIZE,
- _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) | _PAGE_GUARDED);
- }
-
-
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
-{
- ppc4xx_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = redwood5_setup_arch;
- ppc_md.setup_io_mappings = redwood5_map_io;
-}
diff --git a/arch/ppc/platforms/4xx/redwood5.h b/arch/ppc/platforms/4xx/redwood5.h
deleted file mode 100644
index 49edd4818970..000000000000
--- a/arch/ppc/platforms/4xx/redwood5.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Macros, definitions, and data structures specific to the IBM PowerPC
- * STB03xxx "Redwood" evaluation board.
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_REDWOOD5_H__
-#define __ASM_REDWOOD5_H__
-
-/* Redwood5 has an STB04xxx core */
-#include <platforms/4xx/ibmstb4.h>
-
-#ifndef __ASSEMBLY__
-typedef struct board_info {
- unsigned char bi_s_version[4]; /* Version of this structure */
- unsigned char bi_r_version[30]; /* Version of the IBM ROM */
- unsigned int bi_memsize; /* DRAM installed, in bytes */
- unsigned int bi_dummy; /* field shouldn't exist */
- unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
- unsigned int bi_intfreq; /* Processor speed, in Hz */
- unsigned int bi_busfreq; /* Bus speed, in Hz */
- unsigned int bi_tbfreq; /* Software timebase freq */
-} bd_t;
-#endif /* !__ASSEMBLY__ */
-
-
-#define SMC91111_BASE_ADDR 0xf2000300
-#define SMC91111_REG_SIZE 16
-#define SMC91111_IRQ 28
-
-#ifdef MAX_HWIFS
-#undef MAX_HWIFS
-#endif
-#define MAX_HWIFS 1
-
-#define _IO_BASE 0
-#define _ISA_MEM_BASE 0
-#define PCI_DRAM_OFFSET 0
-
-#define BASE_BAUD (378000000 / 18 / 16)
-
-#define PPC4xx_MACHINE_NAME "IBM Redwood5"
-
-#endif /* __ASM_REDWOOD5_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/redwood6.c b/arch/ppc/platforms/4xx/redwood6.c
deleted file mode 100644
index 006e29f83a1a..000000000000
--- a/arch/ppc/platforms/4xx/redwood6.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/pagemap.h>
-#include <linux/platform_device.h>
-#include <linux/ioport.h>
-#include <asm/io.h>
-#include <asm/ppc4xx_pic.h>
-#include <linux/delay.h>
-#include <asm/machdep.h>
-
-/*
- * Define external IRQ senses and polarities.
- */
-unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
-};
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = SMC91111_BASE_ADDR,
- .end = SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = SMC91111_IRQ,
- .end = SMC91111_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-static struct platform_device *redwood6_devs[] __initdata = {
- &smc91x_device,
-};
-
-static int __init
-redwood6_platform_add_devices(void)
-{
- return platform_add_devices(redwood6_devs, ARRAY_SIZE(redwood6_devs));
-}
-
-
-void __init
-redwood6_setup_arch(void)
-{
-#ifdef CONFIG_IDE
- void *xilinx, *xilinx_1, *xilinx_2;
- unsigned short us_reg5;
-#endif
-
- ppc4xx_setup_arch();
-
-#ifdef CONFIG_IDE
- xilinx = (unsigned long) ioremap(IDE_XLINUX_MUX_BASE, 0x10);
- /* init xilinx control registers - enable ide mux, clear reset bit */
- if (!xilinx) {
- printk(KERN_CRIT
- "redwood6_setup_arch() xilinxi ioremap failed\n");
- return;
- }
- xilinx_1 = xilinx + 0xa;
- xilinx_2 = xilinx + 0xe;
-
- us_reg5 = readb(xilinx_1);
- writeb(0x01d1, xilinx_1);
- writeb(0x0008, xilinx_2);
-
- udelay(10 * 1000);
-
- writeb(0x01d1, xilinx_1);
- writeb(0x0008, xilinx_2);
-#endif
-
-#ifdef DEBUG_BRINGUP
- bd_t *bip = (bd_t *) __res;
- printk("\n");
- printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
- printk("\n");
- printk("bi_s_version\t %s\n", bip->bi_s_version);
- printk("bi_r_version\t %s\n", bip->bi_r_version);
- printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
- bip->bi_memsize / (1024 * 1000));
- printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
- bip->bi_enetaddr[0], bip->bi_enetaddr[1], bip->bi_enetaddr[2],
- bip->bi_enetaddr[3], bip->bi_enetaddr[4], bip->bi_enetaddr[5]);
-
- printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
- bip->bi_intfreq, bip->bi_intfreq / 1000000);
-
- printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
- bip->bi_busfreq, bip->bi_busfreq / 1000000);
- printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n",
- bip->bi_tbfreq, bip->bi_tbfreq / 1000000);
-
- printk("\n");
-#endif
-
- /* Identify the system */
- printk(KERN_INFO "IBM Redwood6 (STBx25XX) Platform\n");
- printk(KERN_INFO
- "Port by MontaVista Software, Inc. (source@mvista.com)\n");
-
- device_initcall(redwood6_platform_add_devices);
-}
-
-void __init
-redwood6_map_io(void)
-{
- int i;
-
- ppc4xx_map_io();
- for (i = 0; i < 16; i++) {
- unsigned long v, p;
-
- /* 0x400x0000 -> 0xe00x0000 */
- p = 0x40000000 | (i << 16);
- v = STBx25xx_IO_BASE | (i << 16);
-
- io_block_mapping(v, p, PAGE_SIZE,
- _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) |
- _PAGE_GUARDED);
- }
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
-{
- ppc4xx_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = redwood6_setup_arch;
- ppc_md.setup_io_mappings = redwood6_map_io;
-}
diff --git a/arch/ppc/platforms/4xx/redwood6.h b/arch/ppc/platforms/4xx/redwood6.h
deleted file mode 100644
index 1edcbe5c51c7..000000000000
--- a/arch/ppc/platforms/4xx/redwood6.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Macros, definitions, and data structures specific to the IBM PowerPC
- * STBx25xx "Redwood6" evaluation board.
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_REDWOOD5_H__
-#define __ASM_REDWOOD5_H__
-
-/* Redwood6 has an STBx25xx core */
-#include <platforms/4xx/ibmstbx25.h>
-
-#ifndef __ASSEMBLY__
-typedef struct board_info {
- unsigned char bi_s_version[4]; /* Version of this structure */
- unsigned char bi_r_version[30]; /* Version of the IBM ROM */
- unsigned int bi_memsize; /* DRAM installed, in bytes */
- unsigned int bi_dummy; /* field shouldn't exist */
- unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
- unsigned int bi_intfreq; /* Processor speed, in Hz */
- unsigned int bi_busfreq; /* Bus speed, in Hz */
- unsigned int bi_tbfreq; /* Software timebase freq */
-} bd_t;
-#endif /* !__ASSEMBLY__ */
-
-#define SMC91111_BASE_ADDR 0xf2030300
-#define SMC91111_REG_SIZE 16
-#define SMC91111_IRQ 27
-#define IDE_XLINUX_MUX_BASE 0xf2040000
-#define IDE_DMA_ADDR 0xfce00000
-
-#ifdef MAX_HWIFS
-#undef MAX_HWIFS
-#endif
-#define MAX_HWIFS 1
-
-#define _IO_BASE 0
-#define _ISA_MEM_BASE 0
-#define PCI_DRAM_OFFSET 0
-
-#define BASE_BAUD (378000000 / 18 / 16)
-
-#define PPC4xx_MACHINE_NAME "IBM Redwood6"
-
-#endif /* __ASM_REDWOOD5_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c
deleted file mode 100644
index 8689f3e8ef3a..000000000000
--- a/arch/ppc/platforms/4xx/sycamore.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Architecture- / platform-specific boot-time initialization code for
- * IBM PowerPC 4xx based boards.
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/pci.h>
-#include <linux/rtc.h>
-
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/system.h>
-#include <asm/pci-bridge.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/io.h>
-#include <asm/ibm_ocp_pci.h>
-#include <asm/todc.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-void *kb_cs;
-void *kb_data;
-void *sycamore_rtc_base;
-
-/*
- * Define external IRQ senses and polarities.
- */
-unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 10 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 11 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 12 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
-};
-
-
-/* Some IRQs unique to Sycamore.
- * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
- */
-int __init
-ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
- {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
- {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
- {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
- };
-
- const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-};
-
-void __init
-sycamore_setup_arch(void)
-{
- void *fpga_brdc;
- unsigned char fpga_brdc_data;
- void *fpga_enable;
- void *fpga_polarity;
- void *fpga_status;
- void *fpga_trigger;
-
- ppc4xx_setup_arch();
-
- ibm_ocp_set_emac(0, 0);
-
- kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
- if (!kb_data) {
- printk(KERN_CRIT
- "sycamore_setup_arch() kb_data ioremap failed\n");
- return;
- }
-
- kb_cs = kb_data + 1;
-
- fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
- if (!fpga_status) {
- printk(KERN_CRIT
- "sycamore_setup_arch() fpga_status ioremap failed\n");
- return;
- }
-
- fpga_enable = fpga_status + 1;
- fpga_polarity = fpga_status + 2;
- fpga_trigger = fpga_status + 3;
- fpga_brdc = fpga_status + 4;
-
- /* split the keyboard and mouse interrupts */
- fpga_brdc_data = readb(fpga_brdc);
- fpga_brdc_data |= 0x80;
- writeb(fpga_brdc_data, fpga_brdc);
-
- writeb(0x3, fpga_enable);
-
- writeb(0x3, fpga_polarity);
-
- writeb(0x3, fpga_trigger);
-
- /* RTC step for the sycamore */
- sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
- TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
- sycamore_rtc_base, 8);
-
- /* Identify the system */
- printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
- printk(KERN_INFO
- "Port by MontaVista Software, Inc. (source@mvista.com)\n");
-}
-
-void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
- unsigned int bar_response, bar;
- /*
- * Expected PCI mapping:
- *
- * PLB addr PCI memory addr
- * --------------------- ---------------------
- * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
- * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
- *
- * PLB addr PCI io addr
- * --------------------- ---------------------
- * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
- *
- * The following code is simplified by assuming that the bootrom
- * has been well behaved in following this mapping.
- */
-
-#ifdef DEBUG
- int i;
-
- printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
- printk("PCI bridge regs before fixup \n");
- for (i = 0; i <= 3; i++) {
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
- }
- printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
- printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
- printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
- printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-
- /* added for IBM boot rom version 1.15 bios bar changes -AK */
-
- /* Disable region first */
- out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
- /* PLB starting addr, PCI: 0x80000000 */
- out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
- /* PCI start addr, 0x80000000 */
- out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
- /* 512MB range of PLB to PCI */
- out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
- /* Enable no pre-fetch, enable region */
- out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
- (PPC405_PCI_UPPER_MEM -
- PPC405_PCI_MEM_BASE)) | 0x01));
-
- /* Enable inbound region one - 1GB size */
- out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
-
- /* Disable outbound region one */
- out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-
- /* Disable inbound region two */
- out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
- /* Disable outbound region two */
- out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-
- /* Zero config bars */
- for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
- early_write_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- 0x00000000);
- early_read_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- &bar_response);
- DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
- hose->first_busno, PCI_SLOT(hose->first_busno),
- PCI_FUNC(hose->first_busno), bar, bar_response);
- }
- /* end workaround */
-
-#ifdef DEBUG
- printk("PCI bridge regs after fixup \n");
- for (i = 0; i <= 3; i++) {
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
- }
- printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
- printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
- printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
- printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-#endif
-
-}
-
-void __init
-sycamore_map_io(void)
-{
- ppc4xx_map_io();
- io_block_mapping(SYCAMORE_RTC_VADDR,
- SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
-{
- ppc4xx_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = sycamore_setup_arch;
- ppc_md.setup_io_mappings = sycamore_map_io;
-
-#ifdef CONFIG_GEN_RTC
- ppc_md.time_init = todc_time_init;
- ppc_md.set_rtc_time = todc_set_rtc_time;
- ppc_md.get_rtc_time = todc_get_rtc_time;
- ppc_md.nvram_read_val = todc_direct_read_val;
- ppc_md.nvram_write_val = todc_direct_write_val;
-#endif
-}
diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h
deleted file mode 100644
index 69b169eac053..000000000000
--- a/arch/ppc/platforms/4xx/sycamore.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Sycamore board definitions
- *
- * Copyright (c) 2005 DENX Software Engineering
- * Stefan Roese <sr@denx.de>
- *
- * Based on original work by
- * Armin Kuster <akuster@mvista.com>
- * 2000 (c) MontaVista, Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_SYCAMORE_H__
-#define __ASM_SYCAMORE_H__
-
-#include <platforms/4xx/ibm405gpr.h>
-#include <asm/ppcboot.h>
-
-/* Memory map for the IBM "Sycamore" 405GPr evaluation board.
- * Generic 4xx plus RTC.
- */
-
-#define SYCAMORE_RTC_PADDR ((uint)0xf0000000)
-#define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR
-#define SYCAMORE_RTC_SIZE ((uint)8*1024)
-
-#define BASE_BAUD 691200
-
-#define SYCAMORE_PS2_BASE 0xF0100000
-
-/* Flash */
-#define PPC40x_FPGA_BASE 0xF0300000
-#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */
-#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
-#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
-#define PPC40x_FLASH_LOW 0xFFF00000
-#define PPC40x_FLASH_HIGH 0xFFF80000
-#define PPC40x_FLASH_SIZE 0x80000
-
-#define PPC4xx_MACHINE_NAME "IBM Sycamore"
-
-#endif /* __ASM_SYCAMORE_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c
deleted file mode 100644
index 115694275083..000000000000
--- a/arch/ppc/platforms/4xx/taishan.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * arch/ppc/platforms/4xx/taishan.c
- *
- * AMCC Taishan board specific routines
- *
- * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/ndfc.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/bootinfo.h>
-#include <asm/ppcboot.h>
-
-#include <syslib/gen550.h>
-#include <syslib/ibm440gx_common.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-/*
- * NOR FLASH configuration (using mtd physmap driver)
- */
-
-/* start will be added dynamically, end is always fixed */
-static struct resource taishan_nor_resource = {
- .start = TAISHAN_FLASH_ADDR,
- .end = 0x1ffffffffULL,
- .flags = IORESOURCE_MEM,
-};
-
-#define RW_PART0_OF 0
-#define RW_PART0_SZ 0x180000
-#define RW_PART1_SZ 0x200000
-/* Partition 2 will be autosized dynamically... */
-#define RW_PART3_SZ 0x80000
-#define RW_PART4_SZ 0x40000
-
-static struct mtd_partition taishan_nor_parts[] = {
- {
- .name = "kernel",
- .offset = 0,
- .size = RW_PART0_SZ
- },
- {
- .name = "root",
- .offset = MTDPART_OFS_APPEND,
- .size = RW_PART1_SZ,
- },
- {
- .name = "user",
- .offset = MTDPART_OFS_APPEND,
-/* .size = RW_PART2_SZ */ /* will be adjusted dynamically */
- },
- {
- .name = "env",
- .offset = MTDPART_OFS_APPEND,
- .size = RW_PART3_SZ,
- },
- {
- .name = "u-boot",
- .offset = MTDPART_OFS_APPEND,
- .size = RW_PART4_SZ,
- }
-};
-
-static struct physmap_flash_data taishan_nor_data = {
- .width = 4,
- .parts = taishan_nor_parts,
- .nr_parts = ARRAY_SIZE(taishan_nor_parts),
-};
-
-static struct platform_device taishan_nor_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &taishan_nor_data,
- },
- .num_resources = 1,
- .resource = &taishan_nor_resource,
-};
-
-static int taishan_setup_flash(void)
-{
- /*
- * Adjust partition 2 to flash size
- */
- taishan_nor_parts[2].size = __res.bi_flashsize -
- RW_PART0_SZ - RW_PART1_SZ - RW_PART3_SZ - RW_PART4_SZ;
-
- platform_device_register(&taishan_nor_device);
-
- return 0;
-}
-arch_initcall(taishan_setup_flash);
-
-static void __init
-taishan_calibrate_decr(void)
-{
- unsigned int freq;
-
- if (mfspr(SPRN_CCR1) & CCR1_TCS)
- freq = TAISHAN_TMR_CLK;
- else
- freq = clocks.cpu;
-
- ibm44x_calibrate_decr(freq);
-}
-
-static int
-taishan_show_cpuinfo(struct seq_file *m)
-{
- seq_printf(m, "vendor\t\t: AMCC\n");
- seq_printf(m, "machine\t\t: PPC440GX EVB (Taishan)\n");
- ibm440gx_show_cpuinfo(m);
- return 0;
-}
-
-static inline int
-taishan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 23, 24, 25, 26 }, /* IDSEL 1 - PCI Slot 0 */
- { 24, 25, 26, 23 }, /* IDSEL 2 - PCI Slot 1 */
- };
-
- const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static void __init taishan_set_emacdata(void)
-{
- struct ocp_def *def;
- struct ocp_func_emac_data *emacdata;
- int i;
-
- /* Set phy_map, phy_mode, and mac_addr for each EMAC */
- for (i=2; i<4; i++) {
- def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
- emacdata = def->additions;
- if (i < 2) {
- emacdata->phy_map = 0x00000001; /* Skip 0x00 */
- emacdata->phy_mode = PHY_MODE_SMII;
- } else {
- emacdata->phy_map = 0x00000001; /* Skip 0x00 */
- emacdata->phy_mode = PHY_MODE_RGMII;
- }
- if (i == 0)
- memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
- else if (i == 1)
- memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
- else if (i == 2)
- memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
- else if (i == 3)
- memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
- }
-}
-
-#define PCIX_READW(offset) \
- (readw(pcix_reg_base+offset))
-
-#define PCIX_WRITEW(value, offset) \
- (writew(value, pcix_reg_base+offset))
-
-#define PCIX_WRITEL(value, offset) \
- (writel(value, pcix_reg_base+offset))
-
-/*
- * FIXME: This is only here to "make it work". This will move
- * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
- * configuration library. -Matt
- */
-static void __init
-taishan_setup_pcix(void)
-{
- void *pcix_reg_base;
-
- pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
-
- /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
- PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
-
- /* Disable all windows */
- PCIX_WRITEL(0, PCIX0_POM0SA);
- PCIX_WRITEL(0, PCIX0_POM1SA);
- PCIX_WRITEL(0, PCIX0_POM2SA);
- PCIX_WRITEL(0, PCIX0_PIM0SA);
- PCIX_WRITEL(0, PCIX0_PIM0SAH);
- PCIX_WRITEL(0, PCIX0_PIM1SA);
- PCIX_WRITEL(0, PCIX0_PIM2SA);
- PCIX_WRITEL(0, PCIX0_PIM2SAH);
-
- /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
- PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
- PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
- PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
- PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
- PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
-
- /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
- PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
- PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
- PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
- PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
-
- iounmap(pcix_reg_base);
-
- eieio();
-}
-
-static void __init
-taishan_setup_hose(void)
-{
- struct pci_controller *hose;
-
- /* Configure windows on the PCI-X host bridge */
- taishan_setup_pcix();
-
- hose = pcibios_alloc_controller();
-
- if (!hose)
- return;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- hose->pci_mem_offset = TAISHAN_PCI_MEM_OFFSET;
-
- pci_init_resource(&hose->io_resource,
- TAISHAN_PCI_LOWER_IO,
- TAISHAN_PCI_UPPER_IO,
- IORESOURCE_IO,
- "PCI host bridge");
-
- pci_init_resource(&hose->mem_resources[0],
- TAISHAN_PCI_LOWER_MEM,
- TAISHAN_PCI_UPPER_MEM,
- IORESOURCE_MEM,
- "PCI host bridge");
-
- hose->io_space.start = TAISHAN_PCI_LOWER_IO;
- hose->io_space.end = TAISHAN_PCI_UPPER_IO;
- hose->mem_space.start = TAISHAN_PCI_LOWER_MEM;
- hose->mem_space.end = TAISHAN_PCI_UPPER_MEM;
- hose->io_base_virt = ioremap64(TAISHAN_PCI_IO_BASE, TAISHAN_PCI_IO_SIZE);
- isa_io_base = (unsigned long) hose->io_base_virt;
-
- setup_indirect_pci(hose,
- TAISHAN_PCI_CFGA_PLB32,
- TAISHAN_PCI_CFGD_PLB32);
- hose->set_cfg_type = 1;
-
- hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
- ppc_md.pci_swizzle = common_swizzle;
- ppc_md.pci_map_irq = taishan_map_irq;
-}
-
-
-static void __init
-taishan_early_serial_map(void)
-{
- struct uart_port port;
-
- /* Setup ioremapped serial port access */
- memset(&port, 0, sizeof(port));
- port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
- port.irq = UART0_INT;
- port.uartclk = clocks.uart0;
- port.regshift = 0;
- port.iotype = UPIO_MEM;
- port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- port.line = 0;
-
- if (early_serial_setup(&port) != 0)
- printk("Early serial init of port 0 failed\n");
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- /* Configure debug serial access */
- gen550_init(0, &port);
-
- /* Purge TLB entry added in head_44x.S for early serial access */
- _tlbie(UART0_IO_BASE, 0);
-#endif
-
- port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
- port.irq = UART1_INT;
- port.uartclk = clocks.uart1;
- port.line = 1;
-
- if (early_serial_setup(&port) != 0)
- printk("Early serial init of port 1 failed\n");
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
- /* Configure debug serial access */
- gen550_init(1, &port);
-#endif
-}
-
-static void __init
-taishan_setup_arch(void)
-{
- taishan_set_emacdata();
-
- ibm440gx_tah_enable();
-
- /*
- * Determine various clocks.
- * To be completely correct we should get SysClk
- * from FPGA, because it can be changed by on-board switches
- * --ebs
- */
- ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
- ocp_sys_info.opb_bus_freq = clocks.opb;
-
- /* init to some ~sane value until calibrate_delay() runs */
- loops_per_jiffy = 50000000/HZ;
-
- /* Setup PCI host bridge */
- taishan_setup_hose();
-
-#ifdef CONFIG_BLK_DEV_INITRD
- if (initrd_start)
- ROOT_DEV = Root_RAM0;
- else
-#endif
-#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
-#else
- ROOT_DEV = Root_HDA1;
-#endif
-
- taishan_early_serial_map();
-
- /* Identify the system */
- printk("AMCC PowerPC 440GX Taishan Platform\n");
-}
-
-static void __init taishan_init(void)
-{
- ibm440gx_l2c_setup(&clocks);
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
- unsigned long r5, unsigned long r6, unsigned long r7)
-{
- ibm44x_platform_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = taishan_setup_arch;
- ppc_md.show_cpuinfo = taishan_show_cpuinfo;
- ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
-
- ppc_md.calibrate_decr = taishan_calibrate_decr;
-
-#ifdef CONFIG_KGDB
- ppc_md.early_serial_map = taishan_early_serial_map;
-#endif
- ppc_md.init = taishan_init;
-}
-
diff --git a/arch/ppc/platforms/4xx/taishan.h b/arch/ppc/platforms/4xx/taishan.h
deleted file mode 100644
index ea7561a80457..000000000000
--- a/arch/ppc/platforms/4xx/taishan.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * arch/ppc/platforms/4xx/taishan.h
- *
- * AMCC Taishan board definitions
- *
- * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_TAISHAN_H__
-#define __ASM_TAISHAN_H__
-
-#include <platforms/4xx/ibm440gx.h>
-
-/* External timer clock frequency */
-#define TAISHAN_TMR_CLK 25000000
-
-/* Flash */
-#define TAISHAN_FPGA_ADDR 0x0000000141000000ULL
-#define TAISHAN_LCM_ADDR 0x0000000142000000ULL
-#define TAISHAN_FLASH_ADDR 0x00000001fc000000ULL
-#define TAISHAN_FLASH_SIZE 0x4000000
-
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE 2
-
-/* head_44x.S created UART mapping, used before early_serial_setup.
- * We cannot use default OpenBIOS UART mappings because they
- * don't work for configurations with more than 512M RAM. --ebs
- */
-#define UART0_IO_BASE 0xF0000200
-#define UART1_IO_BASE 0xF0000300
-
-#define BASE_BAUD 11059200/16
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (void*)UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1)
-
-/* PCI support */
-#define TAISHAN_PCI_LOWER_IO 0x00000000
-#define TAISHAN_PCI_UPPER_IO 0x0000ffff
-#define TAISHAN_PCI_LOWER_MEM 0x80000000
-#define TAISHAN_PCI_UPPER_MEM 0xffffefff
-
-#define TAISHAN_PCI_CFGA_PLB32 0x0ec00000
-#define TAISHAN_PCI_CFGD_PLB32 0x0ec00004
-
-#define TAISHAN_PCI_IO_BASE 0x0000000208000000ULL
-#define TAISHAN_PCI_IO_SIZE 0x00010000
-#define TAISHAN_PCI_MEM_OFFSET 0x00000000
-
-#endif /* __ASM_TAISHAN_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h
deleted file mode 100644
index 738280420be5..000000000000
--- a/arch/ppc/platforms/4xx/virtex.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Basic Virtex platform defines, included by <asm/ibm4xx.h>
- *
- * 2005-2007 (c) Secret Lab Technologies Ltd.
- * 2002-2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_VIRTEX_H__
-#define __ASM_VIRTEX_H__
-
-#include <asm/ibm405.h>
-#include <asm/ppcboot.h>
-
-/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy. */
-#if !defined(BASE_BAUD)
- #define BASE_BAUD (0) /* dummy value; not used */
-#endif
-
-#ifndef __ASSEMBLY__
-extern const char* virtex_machine_name;
-#define PPC4xx_MACHINE_NAME (virtex_machine_name)
-#endif /* !__ASSEMBLY__ */
-
-/* We don't need anything mapped. Size of zero will accomplish that. */
-#define PPC4xx_ONB_IO_PADDR 0u
-#define PPC4xx_ONB_IO_VADDR 0u
-#define PPC4xx_ONB_IO_SIZE 0u
-
-#endif /* __ASM_VIRTEX_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c
deleted file mode 100644
index 2f9772340854..000000000000
--- a/arch/ppc/platforms/4xx/walnut.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Architecture- / platform-specific boot-time initialization code for
- * IBM PowerPC 4xx based boards. Adapted from original
- * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
- * <dan@net4x.com>.
- *
- * Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
- *
- * 2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/pci.h>
-#include <linux/rtc.h>
-
-#include <asm/system.h>
-#include <asm/pci-bridge.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/io.h>
-#include <asm/ocp.h>
-#include <asm/ibm_ocp_pci.h>
-#include <asm/todc.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-void *kb_cs;
-void *kb_data;
-void *walnut_rtc_base;
-
-/* Some IRQs unique to Walnut.
- * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
- */
-int __init
-ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
- {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
- {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
- {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
- };
-
- const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-};
-
-void __init
-walnut_setup_arch(void)
-{
-
- void *fpga_brdc;
- unsigned char fpga_brdc_data;
- void *fpga_enable;
- void *fpga_polarity;
- void *fpga_status;
- void *fpga_trigger;
-
- ppc4xx_setup_arch();
-
- ibm_ocp_set_emac(0, 0);
-
- kb_data = ioremap(WALNUT_PS2_BASE, 8);
- if (!kb_data) {
- printk(KERN_CRIT
- "walnut_setup_arch() kb_data ioremap failed\n");
- return;
- }
-
- kb_cs = kb_data + 1;
-
- fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
- if (!fpga_status) {
- printk(KERN_CRIT
- "walnut_setup_arch() fpga_status ioremap failed\n");
- return;
- }
-
- fpga_enable = fpga_status + 1;
- fpga_polarity = fpga_status + 2;
- fpga_trigger = fpga_status + 3;
- fpga_brdc = fpga_status + 4;
-
- /* split the keyboard and mouse interrupts */
- fpga_brdc_data = readb(fpga_brdc);
- fpga_brdc_data |= 0x80;
- writeb(fpga_brdc_data, fpga_brdc);
-
- writeb(0x3, fpga_enable);
-
- writeb(0x3, fpga_polarity);
-
- writeb(0x3, fpga_trigger);
-
- /* RTC step for the walnut */
- walnut_rtc_base = (void *) WALNUT_RTC_VADDR;
- TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base,
- walnut_rtc_base, 8);
- /* Identify the system */
- printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. (source@mvista.com)\n");
-}
-
-void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
- unsigned int bar_response, bar;
- /*
- * Expected PCI mapping:
- *
- * PLB addr PCI memory addr
- * --------------------- ---------------------
- * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
- * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
- *
- * PLB addr PCI io addr
- * --------------------- ---------------------
- * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
- *
- * The following code is simplified by assuming that the bootrom
- * has been well behaved in following this mapping.
- */
-
-#ifdef DEBUG
- int i;
-
- printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
- printk("PCI bridge regs before fixup \n");
- for (i = 0; i <= 3; i++) {
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
- }
- printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
- printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
- printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
- printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-
- /* added for IBM boot rom version 1.15 bios bar changes -AK */
-
- /* Disable region first */
- out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
- /* PLB starting addr, PCI: 0x80000000 */
- out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
- /* PCI start addr, 0x80000000 */
- out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
- /* 512MB range of PLB to PCI */
- out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
- /* Enable no pre-fetch, enable region */
- out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
- (PPC405_PCI_UPPER_MEM -
- PPC405_PCI_MEM_BASE)) | 0x01));
-
- /* Disable region one */
- out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
- out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
- out_le32((void *) &(pcip->ptm1ms), 0x00000000);
-
- /* Disable region two */
- out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
- out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
- out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
- /* Zero config bars */
- for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
- early_write_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- 0x00000000);
- early_read_config_dword(hose, hose->first_busno,
- PCI_FUNC(hose->first_busno), bar,
- &bar_response);
- DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
- hose->first_busno, PCI_SLOT(hose->first_busno),
- PCI_FUNC(hose->first_busno), bar, bar_response);
- }
- /* end work around */
-
-#ifdef DEBUG
- printk("PCI bridge regs after fixup \n");
- for (i = 0; i <= 3; i++) {
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
- printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
- }
- printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
- printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
- printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
- printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-#endif
-}
-
-void __init
-walnut_map_io(void)
-{
- ppc4xx_map_io();
- io_block_mapping(WALNUT_RTC_VADDR,
- WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
-{
- ppc4xx_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = walnut_setup_arch;
- ppc_md.setup_io_mappings = walnut_map_io;
-
-#ifdef CONFIG_GEN_RTC
- ppc_md.time_init = todc_time_init;
- ppc_md.set_rtc_time = todc_set_rtc_time;
- ppc_md.get_rtc_time = todc_get_rtc_time;
- ppc_md.nvram_read_val = todc_direct_read_val;
- ppc_md.nvram_write_val = todc_direct_write_val;
-#endif
-}
diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h
deleted file mode 100644
index d9c4eb788940..000000000000
--- a/arch/ppc/platforms/4xx/walnut.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Walnut board definitions
- *
- * Copyright (c) 2005 DENX Software Engineering
- * Stefan Roese <sr@denx.de>
- *
- * Based on original work by
- * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
- * Frank Rowand <frank_rowand@mvista.com>
- * Debbie Chu <debbie_chu@mvista.com>
- * 2000 (c) MontaVista, Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_WALNUT_H__
-#define __ASM_WALNUT_H__
-
-#include <platforms/4xx/ibm405gp.h>
-#include <asm/ppcboot.h>
-
-/* Memory map for the IBM "Walnut" 405GP evaluation board.
- * Generic 4xx plus RTC.
- */
-
-#define WALNUT_RTC_PADDR ((uint)0xf0000000)
-#define WALNUT_RTC_VADDR WALNUT_RTC_PADDR
-#define WALNUT_RTC_SIZE ((uint)8*1024)
-
-#define BASE_BAUD 691200
-
-#define WALNUT_PS2_BASE 0xF0100000
-
-/* Flash */
-#define PPC40x_FPGA_BASE 0xF0300000
-#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */
-#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
-#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
-#define PPC40x_FLASH_LOW 0xFFF00000
-#define PPC40x_FLASH_HIGH 0xFFF80000
-#define PPC40x_FLASH_SIZE 0x80000
-#define WALNUT_FPGA_BASE PPC40x_FPGA_BASE
-
-#define PPC4xx_MACHINE_NAME "IBM Walnut"
-
-#endif /* __ASM_WALNUT_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c
deleted file mode 100644
index 6e522fefc26f..000000000000
--- a/arch/ppc/platforms/4xx/xilinx_ml300.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Xilinx ML300 evaluation board initialization
- *
- * Author: MontaVista Software, Inc.
- * source@mvista.com
- *
- * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/serialP.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-
-#include <syslib/gen550.h>
-#include <syslib/virtex_devices.h>
-#include <platforms/4xx/xparameters/xparameters.h>
-
-/*
- * As an overview of how the following functions (platform_init,
- * ml300_map_io, ml300_setup_arch and ml300_init_IRQ) fit into the
- * kernel startup procedure, here's a call tree:
- *
- * start_here arch/ppc/kernel/head_4xx.S
- * early_init arch/ppc/kernel/setup.c
- * machine_init arch/ppc/kernel/setup.c
- * platform_init this file
- * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c
- * parse_bootinfo
- * find_bootinfo
- * "setup some default ppc_md pointers"
- * MMU_init arch/ppc/mm/init.c
- * *ppc_md.setup_io_mappings == ml300_map_io this file
- * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c
- * start_kernel init/main.c
- * setup_arch arch/ppc/kernel/setup.c
- * #if defined(CONFIG_KGDB)
- * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
- * #endif
- * *ppc_md.setup_arch == ml300_setup_arch this file
- * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c
- * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c
- * init_IRQ arch/ppc/kernel/irq.c
- * *ppc_md.init_IRQ == ml300_init_IRQ this file
- * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c
- * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c
- */
-
-const char* virtex_machine_name = "ML300 Reference Design";
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
-static volatile unsigned *powerdown_base =
- (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
-
-static void
-xilinx_power_off(void)
-{
- local_irq_disable();
- out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
- while (1) ;
-}
-#endif
-
-void __init
-ml300_map_io(void)
-{
- ppc4xx_map_io();
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
- powerdown_base = ioremap((unsigned long) powerdown_base,
- XPAR_POWER_0_POWERDOWN_HIGHADDR -
- XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
-#endif
-}
-
-void __init
-ml300_setup_arch(void)
-{
- virtex_early_serial_map();
- ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */
-
- /* Identify the system */
- printk(KERN_INFO "Xilinx ML300 Reference System (Virtex-II Pro)\n");
-}
-
-/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
-void __init
-ml300_init_irq(void)
-{
- ppc4xx_init_IRQ();
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
-{
- ppc4xx_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = ml300_setup_arch;
- ppc_md.setup_io_mappings = ml300_map_io;
- ppc_md.init_IRQ = ml300_init_irq;
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
- ppc_md.power_off = xilinx_power_off;
-#endif
-
-#ifdef CONFIG_KGDB
- ppc_md.early_serial_map = virtex_early_serial_map;
-#endif
-}
-
diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.c b/arch/ppc/platforms/4xx/xilinx_ml403.c
deleted file mode 100644
index bc3ace3762e7..000000000000
--- a/arch/ppc/platforms/4xx/xilinx_ml403.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Xilinx ML403 evaluation board initialization
- *
- * Author: Grant Likely <grant.likely@secretlab.ca>
- *
- * 2005-2007 (c) Secret Lab Technologies Ltd.
- * 2002-2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/serialP.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-
-#include <syslib/gen550.h>
-#include <syslib/virtex_devices.h>
-#include <platforms/4xx/xparameters/xparameters.h>
-
-/*
- * As an overview of how the following functions (platform_init,
- * ml403_map_io, ml403_setup_arch and ml403_init_IRQ) fit into the
- * kernel startup procedure, here's a call tree:
- *
- * start_here arch/ppc/kernel/head_4xx.S
- * early_init arch/ppc/kernel/setup.c
- * machine_init arch/ppc/kernel/setup.c
- * platform_init this file
- * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c
- * parse_bootinfo
- * find_bootinfo
- * "setup some default ppc_md pointers"
- * MMU_init arch/ppc/mm/init.c
- * *ppc_md.setup_io_mappings == ml403_map_io this file
- * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c
- * start_kernel init/main.c
- * setup_arch arch/ppc/kernel/setup.c
- * #if defined(CONFIG_KGDB)
- * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
- * #endif
- * *ppc_md.setup_arch == ml403_setup_arch this file
- * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c
- * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c
- * init_IRQ arch/ppc/kernel/irq.c
- * *ppc_md.init_IRQ == ml403_init_IRQ this file
- * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c
- * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c
- */
-
-const char* virtex_machine_name = "ML403 Reference Design";
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
-static volatile unsigned *powerdown_base =
- (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
-
-static void
-xilinx_power_off(void)
-{
- local_irq_disable();
- out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
- while (1) ;
-}
-#endif
-
-void __init
-ml403_map_io(void)
-{
- ppc4xx_map_io();
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
- powerdown_base = ioremap((unsigned long) powerdown_base,
- XPAR_POWER_0_POWERDOWN_HIGHADDR -
- XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
-#endif
-}
-
-void __init
-ml403_setup_arch(void)
-{
- virtex_early_serial_map();
- ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */
-
- /* Identify the system */
- printk(KERN_INFO "Xilinx ML403 Reference System (Virtex-4 FX)\n");
-}
-
-/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
-void __init
-ml403_init_irq(void)
-{
- ppc4xx_init_IRQ();
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
-{
- ppc4xx_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = ml403_setup_arch;
- ppc_md.setup_io_mappings = ml403_map_io;
- ppc_md.init_IRQ = ml403_init_irq;
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
- ppc_md.power_off = xilinx_power_off;
-#endif
-
-#ifdef CONFIG_KGDB
- ppc_md.early_serial_map = virtex_early_serial_map;
-#endif
-}
-
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h
deleted file mode 100644
index 650888b00fb0..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * arch/ppc/platforms/4xx/xparameters/xparameters.h
- *
- * This file includes the correct xparameters.h for the CONFIG'ed board plus
- * fixups to translate board specific XPAR values to a common set of names
- *
- * Author: MontaVista Software, Inc.
- * source@mvista.com
- *
- * 2004 (c) MontaVista Software, Inc. This file is licensed under the terms
- * of the GNU General Public License version 2. This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-
-#if defined(CONFIG_XILINX_ML300)
- #include "xparameters_ml300.h"
- #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
- XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
- #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
- XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
-#elif defined(CONFIG_XILINX_ML403)
- #include "xparameters_ml403.h"
- #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
- XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
- #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
- XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
-#else
- /* Add other board xparameter includes here before the #else */
- #error No xparameters_*.h file included
-#endif
-
-#ifndef SERIAL_PORT_DFNS
- /* zImage serial port definitions */
- #define RS_TABLE_SIZE 1
- #define SERIAL_PORT_DFNS { \
- .baud_base = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16, \
- .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, \
- .flags = ASYNC_BOOT_AUTOCONF, \
- .iomem_base = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3, \
- .iomem_reg_shift = 2, \
- .io_type = SERIAL_IO_MEM, \
- },
-#endif
-
-/*
- * A few reasonable defaults for the #defines which could be missing depending
- * on the IP version or variant (e.g. OPB vs PLB)
- */
-
-#ifndef XPAR_EMAC_0_CAM_EXIST
-#define XPAR_EMAC_0_CAM_EXIST 0
-#endif
-#ifndef XPAR_EMAC_0_JUMBO_EXIST
-#define XPAR_EMAC_0_JUMBO_EXIST 0
-#endif
-#ifndef XPAR_EMAC_0_TX_DRE_TYPE
-#define XPAR_EMAC_0_TX_DRE_TYPE 0
-#endif
-#ifndef XPAR_EMAC_0_RX_DRE_TYPE
-#define XPAR_EMAC_0_RX_DRE_TYPE 0
-#endif
-#ifndef XPAR_EMAC_0_TX_INCLUDE_CSUM
-#define XPAR_EMAC_0_TX_INCLUDE_CSUM 0
-#endif
-#ifndef XPAR_EMAC_0_RX_INCLUDE_CSUM
-#define XPAR_EMAC_0_RX_INCLUDE_CSUM 0
-#endif
-
-#ifndef XPAR_EMAC_1_CAM_EXIST
-#define XPAR_EMAC_1_CAM_EXIST 0
-#endif
-#ifndef XPAR_EMAC_1_JUMBO_EXIST
-#define XPAR_EMAC_1_JUMBO_EXIST 0
-#endif
-#ifndef XPAR_EMAC_1_TX_DRE_TYPE
-#define XPAR_EMAC_1_TX_DRE_TYPE 0
-#endif
-#ifndef XPAR_EMAC_1_RX_DRE_TYPE
-#define XPAR_EMAC_1_RX_DRE_TYPE 0
-#endif
-#ifndef XPAR_EMAC_1_TX_INCLUDE_CSUM
-#define XPAR_EMAC_1_TX_INCLUDE_CSUM 0
-#endif
-#ifndef XPAR_EMAC_1_RX_INCLUDE_CSUM
-#define XPAR_EMAC_1_RX_INCLUDE_CSUM 0
-#endif
-
-#ifndef XPAR_GPIO_0_IS_DUAL
-#define XPAR_GPIO_0_IS_DUAL 0
-#endif
-#ifndef XPAR_GPIO_1_IS_DUAL
-#define XPAR_GPIO_1_IS_DUAL 0
-#endif
-#ifndef XPAR_GPIO_2_IS_DUAL
-#define XPAR_GPIO_2_IS_DUAL 0
-#endif
-#ifndef XPAR_GPIO_3_IS_DUAL
-#define XPAR_GPIO_3_IS_DUAL 0
-#endif
-#ifndef XPAR_GPIO_4_IS_DUAL
-#define XPAR_GPIO_4_IS_DUAL 0
-#endif
-
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
deleted file mode 100644
index 97e3f4d4bd54..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*******************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* Description: Driver parameters
-*
-*******************************************************************/
-
-#define XPAR_XPCI_NUM_INSTANCES 1
-#define XPAR_XPCI_CLOCK_HZ 33333333
-#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0
-#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000
-#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF
-#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000
-#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004
-#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000
-#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000
-#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF
-#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000
-#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF
-
-/******************************************************************/
-
-#define XPAR_XEMAC_NUM_INSTANCES 1
-#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
-
-/******************************************************************/
-
-#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0
-#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000
-#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7)
-#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1
-#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8)
-#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F)
-#define XPAR_XGPIO_NUM_INSTANCES 2
-
-/******************************************************************/
-
-#define XPAR_XIIC_NUM_INSTANCES 1
-#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
-#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
-#define XPAR_OPB_IIC_0_DEVICE_ID 0
-#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
-
-/******************************************************************/
-
-#define XPAR_XUARTNS550_NUM_INSTANCES 2
-#define XPAR_XUARTNS550_CLOCK_HZ 100000000
-#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
-#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
-#define XPAR_OPB_UART16550_0_DEVICE_ID 0
-#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000
-#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF
-#define XPAR_OPB_UART16550_1_DEVICE_ID 1
-
-/******************************************************************/
-
-#define XPAR_XSPI_NUM_INSTANCES 1
-#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000
-#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F
-#define XPAR_OPB_SPI_0_DEVICE_ID 0
-#define XPAR_OPB_SPI_0_FIFO_EXIST 1
-#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0
-#define XPAR_OPB_SPI_0_NUM_SS_BITS 1
-
-/******************************************************************/
-
-#define XPAR_XPS2_NUM_INSTANCES 2
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
-
-/******************************************************************/
-
-#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
-#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000
-#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007
-#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
-#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000
-#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF
-#define XPAR_PLB_DDR_0_BASEADDR 0x00000000
-#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF
-
-/******************************************************************/
-
-#define XPAR_XINTC_HAS_IPR 1
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18
-#define XPAR_XINTC_USE_DCR 0
-#define XPAR_XINTC_NUM_INSTANCES 1
-#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0
-#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF
-#define XPAR_DCR_INTC_0_DEVICE_ID 0
-#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000
-
-/******************************************************************/
-
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0
-#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3
-#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4
-#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5
-#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6
-#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7
-#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
-#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9
-#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10
-#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11
-#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12
-#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13
-#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14
-#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15
-#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16
-#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17
-
-/******************************************************************/
-
-#define XPAR_XTFT_NUM_INSTANCES 1
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
-#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_XSYSACE_MEM_WIDTH 8
-#define XPAR_XSYSACE_NUM_INSTANCES 1
-#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
-#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
-#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
-#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8
-
-/******************************************************************/
-
-#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
-
-/******************************************************************/
-
-/******************************************************************/
-
-/* Linux Redefines */
-
-/******************************************************************/
-
-#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
-#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
-#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
-#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000)
-#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR
-#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
-#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_GPIO_0_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_0
-#define XPAR_GPIO_0_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_0
-#define XPAR_GPIO_0_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_0
-#define XPAR_GPIO_1_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_1
-#define XPAR_GPIO_1_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_1
-#define XPAR_GPIO_1_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_1
-
-/******************************************************************/
-
-#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
-#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
-#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
-#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
-#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
-#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_INTC_0_BASEADDR XPAR_DCR_INTC_0_BASEADDR
-#define XPAR_INTC_0_HIGHADDR XPAR_DCR_INTC_0_HIGHADDR
-#define XPAR_INTC_0_KIND_OF_INTR XPAR_DCR_INTC_0_KIND_OF_INTR
-#define XPAR_INTC_0_DEVICE_ID XPAR_DCR_INTC_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
-#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_UARTNS550_1_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
-#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
-#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_TOUCHSCREEN_0_VEC_ID XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR
-#define XPAR_INTC_0_PCI_0_VEC_ID_A XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
-#define XPAR_INTC_0_PCI_0_VEC_ID_B XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
-#define XPAR_INTC_0_PCI_0_VEC_ID_C XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
-#define XPAR_INTC_0_PCI_0_VEC_ID_D XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
-
-/******************************************************************/
-
-#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
-#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
-#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
-#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
-#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
-#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_SPI_0_BASEADDR XPAR_OPB_SPI_0_BASEADDR
-#define XPAR_SPI_0_HIGHADDR XPAR_OPB_SPI_0_HIGHADDR
-#define XPAR_SPI_0_DEVICE_ID XPAR_OPB_SPI_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_TOUCHSCREEN_0_BASEADDR XPAR_OPB_TSD_REF_0_BASEADDR
-#define XPAR_TOUCHSCREEN_0_HIGHADDR XPAR_OPB_TSD_REF_0_HIGHADDR
-#define XPAR_TOUCHSCREEN_0_DEVICE_ID XPAR_OPB_TSD_REF_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
-
-/******************************************************************/
-
-#define XPAR_PCI_0_BASEADDR XPAR_OPB_PCI_REF_0_BASEADDR
-#define XPAR_PCI_0_HIGHADDR XPAR_OPB_PCI_REF_0_HIGHADDR
-#define XPAR_PCI_0_CONFIG_ADDR XPAR_OPB_PCI_REF_0_CONFIG_ADDR
-#define XPAR_PCI_0_CONFIG_DATA XPAR_OPB_PCI_REF_0_CONFIG_DATA
-#define XPAR_PCI_0_LCONFIG_ADDR XPAR_OPB_PCI_REF_0_LCONFIG_ADDR
-#define XPAR_PCI_0_MEM_BASEADDR XPAR_OPB_PCI_REF_0_MEM_BASEADDR
-#define XPAR_PCI_0_MEM_HIGHADDR XPAR_OPB_PCI_REF_0_MEM_HIGHADDR
-#define XPAR_PCI_0_IO_BASEADDR XPAR_OPB_PCI_REF_0_IO_BASEADDR
-#define XPAR_PCI_0_IO_HIGHADDR XPAR_OPB_PCI_REF_0_IO_HIGHADDR
-#define XPAR_PCI_0_CLOCK_FREQ_HZ XPAR_XPCI_CLOCK_HZ
-#define XPAR_PCI_0_DEVICE_ID XPAR_OPB_PCI_REF_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
-#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
-#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
-#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
-#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
-#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
-
-/******************************************************************/
-
-#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
-#define XPAR_DDR_0_SIZE 0x08000000
-
-/******************************************************************/
-
-#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
-#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
-#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
-
-/******************************************************************/
-
-#define XPAR_POWER_0_POWERDOWN_BASEADDR 0x90000004
-#define XPAR_POWER_0_POWERDOWN_HIGHADDR 0x90000007
-#define XPAR_POWER_0_POWERDOWN_VALUE 0xFF
-
-/******************************************************************/
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
deleted file mode 100644
index 5cacdcb3964d..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
+++ /dev/null
@@ -1,243 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by libgen.
-* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
-* DO NOT EDIT.
-*
-* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
-*
-* Description: Driver parameters
-*
-*******************************************************************/
-
-#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000
-#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF
-
-/******************************************************************/
-
-#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000
-#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF
-#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000
-#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
-#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000
-#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF
-#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000
-#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF
-
-/******************************************************************/
-
-#define XPAR_XEMAC_NUM_INSTANCES 1
-#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
-
-/******************************************************************/
-
-#define XPAR_XUARTNS550_NUM_INSTANCES 1
-#define XPAR_XUARTNS550_CLOCK_HZ 100000000
-#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
-#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
-#define XPAR_OPB_UART16550_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_XGPIO_NUM_INSTANCES 3
-#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000
-#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF
-#define XPAR_OPB_GPIO_0_DEVICE_ID 0
-#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_OPB_GPIO_0_IS_DUAL 1
-#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000
-#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF
-#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1
-#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0
-#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1
-#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000
-#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF
-#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2
-#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0
-#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0
-
-/******************************************************************/
-
-#define XPAR_XPS2_NUM_INSTANCES 2
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
-
-/******************************************************************/
-
-#define XPAR_XIIC_NUM_INSTANCES 1
-#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
-#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
-#define XPAR_OPB_IIC_0_DEVICE_ID 0
-#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
-#define XPAR_OPB_IIC_0_GPO_WIDTH 1
-
-/******************************************************************/
-
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10
-#define XPAR_XINTC_HAS_IPR 1
-#define XPAR_XINTC_USE_DCR 0
-#define XPAR_XINTC_NUM_INSTANCES 1
-#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0
-#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF
-#define XPAR_OPB_INTC_0_DEVICE_ID 0
-#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000
-
-/******************************************************************/
-
-#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0
-#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF
-#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
-#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001
-#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0
-#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002
-#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1
-#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004
-#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2
-#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008
-#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010
-#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020
-#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5
-#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040
-#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6
-#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080
-#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7
-#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100
-#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
-#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200
-#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9
-
-/******************************************************************/
-
-#define XPAR_XTFT_NUM_INSTANCES 1
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
-#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_XSYSACE_MEM_WIDTH 16
-#define XPAR_XSYSACE_NUM_INSTANCES 1
-#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
-#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
-#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
-#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16
-
-/******************************************************************/
-
-#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
-
-/******************************************************************/
-
-
-/******************************************************************/
-
-/* Linux Redefines */
-
-/******************************************************************/
-
-#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
-#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
-#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR
-#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR
-#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR
-#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
-#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
-#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
-#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
-
-/******************************************************************/
-
-#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
-
-/******************************************************************/
-
-#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
-#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
-#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
-#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
-#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
-#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0
-#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0
-#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0
-#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1
-#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1
-#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1
-#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0
-#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0
-#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0
-#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1
-#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1
-#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1
-#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR
-#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR
-#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
-#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
-#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
-#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
-#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
-#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
-
-/******************************************************************/
-
-#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
-#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
-#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
-#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
-#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
-#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
-#define XPAR_DDR_0_SIZE 0x4000000
-
-/******************************************************************/
-
-#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
-#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
-#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
-
-/******************************************************************/
-
-#define XPAR_PCI_0_CLOCK_FREQ_HZ 0
-
-/******************************************************************/
-
diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c
deleted file mode 100644
index f6cfd44281fc..000000000000
--- a/arch/ppc/platforms/4xx/yucca.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
- * Yucca board specific routines
- *
- * Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter)
- *
- * Copyright 2004-2005 MontaVista Software Inc.
- * Copyright (c) 2005 Cisco Systems. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/pci-bridge.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/ppcboot.h>
-
-#include <syslib/ibm44x_common.h>
-#include <syslib/ibm440gx_common.h>
-#include <syslib/ibm440sp_common.h>
-#include <syslib/ppc440spe_pcie.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-static void __init
-yucca_calibrate_decr(void)
-{
- unsigned int freq;
-
- if (mfspr(SPRN_CCR1) & CCR1_TCS)
- freq = YUCCA_TMR_CLK;
- else
- freq = clocks.cpu;
-
- ibm44x_calibrate_decr(freq);
-}
-
-static int
-yucca_show_cpuinfo(struct seq_file *m)
-{
- seq_printf(m, "vendor\t\t: AMCC\n");
- seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n");
-
- return 0;
-}
-
-static enum {
- HOSE_UNKNOWN,
- HOSE_PCIX,
- HOSE_PCIE0,
- HOSE_PCIE1,
- HOSE_PCIE2
-} hose_type[4];
-
-static inline int
-yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
-
- if (hose_type[hose->index] == HOSE_PCIX) {
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 81, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */
- };
- const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
- } else if (hose_type[hose->index] == HOSE_PCIE0) {
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 96, 97, 98, 99 },
- };
- const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
- } else if (hose_type[hose->index] == HOSE_PCIE1) {
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 100, 101, 102, 103 },
- };
- const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
- } else if (hose_type[hose->index] == HOSE_PCIE2) {
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 104, 105, 106, 107 },
- };
- const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
- }
- return -1;
-}
-
-static void __init yucca_set_emacdata(void)
-{
- struct ocp_def *def;
- struct ocp_func_emac_data *emacdata;
-
- /* Set phy_map, phy_mode, and mac_addr for the EMAC */
- def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
- emacdata = def->additions;
- emacdata->phy_map = 0x00000001; /* Skip 0x00 */
- emacdata->phy_mode = PHY_MODE_GMII;
- memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
-}
-
-static int __init yucca_pcie_card_present(int port)
-{
- void __iomem *pcie_fpga_base;
- u16 reg;
-
- pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
- reg = in_be16(pcie_fpga_base + FPGA_REG1C);
- iounmap(pcie_fpga_base);
-
- switch(port) {
- case 0: return !(reg & FPGA_REG1C_PE0_PRSNT);
- case 1: return !(reg & FPGA_REG1C_PE1_PRSNT);
- case 2: return !(reg & FPGA_REG1C_PE2_PRSNT);
- default: return 0;
- }
-}
-
-/*
- * For the given slot, set rootpoint mode, send power to the slot,
- * turn on the green LED and turn off the yellow LED, enable the clock
- * and turn off reset.
- */
-static void __init yucca_setup_pcie_fpga_rootpoint(int port)
-{
- void __iomem *pcie_reg_fpga_base;
- u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
-
- pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
-
- switch(port) {
- case 0:
- rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
- endpoint = 0;
- power = FPGA_REG1A_PE0_PWRON;
- green_led = FPGA_REG1A_PE0_GLED;
- clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
- yellow_led = FPGA_REG1A_PE0_YLED;
- reset_off = FPGA_REG1C_PE0_PERST;
- break;
- case 1:
- rootpoint = 0;
- endpoint = FPGA_REG1C_PE1_ENDPOINT;
- power = FPGA_REG1A_PE1_PWRON;
- green_led = FPGA_REG1A_PE1_GLED;
- clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
- yellow_led = FPGA_REG1A_PE1_YLED;
- reset_off = FPGA_REG1C_PE1_PERST;
- break;
- case 2:
- rootpoint = 0;
- endpoint = FPGA_REG1C_PE2_ENDPOINT;
- power = FPGA_REG1A_PE2_PWRON;
- green_led = FPGA_REG1A_PE2_GLED;
- clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
- yellow_led = FPGA_REG1A_PE2_YLED;
- reset_off = FPGA_REG1C_PE2_PERST;
- break;
-
- default:
- iounmap(pcie_reg_fpga_base);
- return;
- }
-
- out_be16(pcie_reg_fpga_base + FPGA_REG1A,
- ~(power | clock | green_led) &
- (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A)));
- out_be16(pcie_reg_fpga_base + FPGA_REG1C,
- ~(endpoint | reset_off) &
- (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C)));
-
- /*
- * Leave device in reset for a while after powering on the
- * slot to give it a chance to initialize.
- */
- mdelay(250);
-
- out_be16(pcie_reg_fpga_base + FPGA_REG1C,
- reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C));
-
- iounmap(pcie_reg_fpga_base);
-}
-
-static void __init
-yucca_setup_hoses(void)
-{
- struct pci_controller *hose;
- char name[20];
- int i;
-
- if (0 && ppc440spe_init_pcie()) {
- printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
- return;
- }
-
- for (i = 0; i <= 2; ++i) {
- if (!yucca_pcie_card_present(i))
- continue;
-
- printk(KERN_INFO "PCIE%d: card present\n", i);
- yucca_setup_pcie_fpga_rootpoint(i);
- if (ppc440spe_init_pcie_rootport(i)) {
- printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
- continue;
- }
-
- hose = pcibios_alloc_controller();
- if (!hose)
- return;
-
- sprintf(name, "PCIE%d host bridge", i);
- pci_init_resource(&hose->io_resource,
- YUCCA_PCIX_LOWER_IO,
- YUCCA_PCIX_UPPER_IO,
- IORESOURCE_IO,
- name);
-
- hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
- i * YUCCA_PCIE_MEM_SIZE;
- hose->mem_space.end = hose->mem_space.start +
- YUCCA_PCIE_MEM_SIZE - 1;
-
- pci_init_resource(&hose->mem_resources[0],
- hose->mem_space.start,
- hose->mem_space.end,
- IORESOURCE_MEM,
- name);
-
- hose->first_busno = 0;
- hose->last_busno = 15;
- hose_type[hose->index] = HOSE_PCIE0 + i;
-
- ppc440spe_setup_pcie(hose, i);
- hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
- }
-
- ppc_md.pci_swizzle = common_swizzle;
- ppc_md.pci_map_irq = yucca_map_irq;
-}
-
-TODC_ALLOC();
-
-static void __init
-yucca_early_serial_map(void)
-{
- struct uart_port port;
-
- /* Setup ioremapped serial port access */
- memset(&port, 0, sizeof(port));
- port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8);
- port.irq = UART0_INT;
- port.uartclk = clocks.uart0;
- port.regshift = 0;
- port.iotype = UPIO_MEM;
- port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
- port.line = 0;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 0 failed\n");
- }
-
- port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8);
- port.irq = UART1_INT;
- port.uartclk = clocks.uart1;
- port.line = 1;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 1 failed\n");
- }
-
- port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8);
- port.irq = UART2_INT;
- port.uartclk = BASE_BAUD;
- port.line = 2;
-
- if (early_serial_setup(&port) != 0) {
- printk("Early serial init of port 2 failed\n");
- }
-}
-
-static void __init
-yucca_setup_arch(void)
-{
- yucca_set_emacdata();
-
-#if !defined(CONFIG_BDI_SWITCH)
- /*
- * The Abatron BDI JTAG debugger does not tolerate others
- * mucking with the debug registers.
- */
- mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
-#endif
-
- /*
- * Determine various clocks.
- * To be completely correct we should get SysClk
- * from FPGA, because it can be changed by on-board switches
- * --ebs
- */
- /* 440GX and 440SPe clocking is the same - rd */
- ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
- ocp_sys_info.opb_bus_freq = clocks.opb;
-
- /* init to some ~sane value until calibrate_delay() runs */
- loops_per_jiffy = 50000000/HZ;
-
- /* Setup PCIXn host bridges */
- yucca_setup_hoses();
-
-#ifdef CONFIG_BLK_DEV_INITRD
- if (initrd_start)
- ROOT_DEV = Root_RAM0;
- else
-#endif
-#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
-#else
- ROOT_DEV = Root_HDA1;
-#endif
-
- yucca_early_serial_map();
-
- /* Identify the system */
- printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n");
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
- unsigned long r5, unsigned long r6, unsigned long r7)
-{
- ibm44x_platform_init(r3, r4, r5, r6, r7);
-
- ppc_md.setup_arch = yucca_setup_arch;
- ppc_md.show_cpuinfo = yucca_show_cpuinfo;
- ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
- ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
-
- ppc_md.calibrate_decr = yucca_calibrate_decr;
-#ifdef CONFIG_KGDB
- ppc_md.early_serial_map = yucca_early_serial_map;
-#endif
-}
diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h
deleted file mode 100644
index bc9684e66a84..000000000000
--- a/arch/ppc/platforms/4xx/yucca.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Yucca board definitions
- *
- * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter)
- *
- * Copyright 2004-2005 MontaVista Software Inc.
- * Copyright (c) 2005 Cisco Systems. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_YUCCA_H__
-#define __ASM_YUCCA_H__
-
-#include <platforms/4xx/ppc440spe.h>
-
-/* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0 0xa0000800
-
-/* Location of MAC addresses in PIBS image */
-#define PIBS_FLASH_BASE 0xffe00000
-#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400)
-
-/* External timer clock frequency */
-#define YUCCA_TMR_CLK 25000000
-
-/*
- * FPGA registers
- */
-#define YUCCA_FPGA_REG_BASE 0x00000004e2000000ULL
-#define YUCCA_FPGA_REG_SIZE 0x24
-
-#define FPGA_REG1A 0x1a
-
-#define FPGA_REG1A_PE0_GLED 0x8000
-#define FPGA_REG1A_PE1_GLED 0x4000
-#define FPGA_REG1A_PE2_GLED 0x2000
-#define FPGA_REG1A_PE0_YLED 0x1000
-#define FPGA_REG1A_PE1_YLED 0x0800
-#define FPGA_REG1A_PE2_YLED 0x0400
-#define FPGA_REG1A_PE0_PWRON 0x0200
-#define FPGA_REG1A_PE1_PWRON 0x0100
-#define FPGA_REG1A_PE2_PWRON 0x0080
-#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
-#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
-#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
-#define FPGA_REG1A_PE_SPREAD0 0x0008
-#define FPGA_REG1A_PE_SPREAD1 0x0004
-#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
-#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
-
-#define FPGA_REG1C 0x1c
-
-#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
-#define FPGA_REG1C_PE1_ENDPOINT 0x4000
-#define FPGA_REG1C_PE2_ENDPOINT 0x2000
-#define FPGA_REG1C_PE0_PRSNT 0x1000
-#define FPGA_REG1C_PE1_PRSNT 0x0800
-#define FPGA_REG1C_PE2_PRSNT 0x0400
-#define FPGA_REG1C_PE0_WAKE 0x0080
-#define FPGA_REG1C_PE1_WAKE 0x0040
-#define FPGA_REG1C_PE2_WAKE 0x0020
-#define FPGA_REG1C_PE0_PERST 0x0010
-#define FPGA_REG1C_PE1_PERST 0x0008
-#define FPGA_REG1C_PE2_PERST 0x0004
-
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE 3
-
-/* PIBS defined UART mappings, used before early_serial_setup */
-#define UART0_IO_BASE 0xa0000200
-#define UART1_IO_BASE 0xa0000300
-#define UART2_IO_BASE 0xa0000600
-
-#define BASE_BAUD 11059200
-#define STD_UART_OP(num) \
- { 0, BASE_BAUD, 0, UART##num##_INT, \
- (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: (void*)UART##num##_IO_BASE, \
- io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS \
- STD_UART_OP(0) \
- STD_UART_OP(1) \
- STD_UART_OP(2)
-
-/* PCI support */
-#define YUCCA_PCIX_LOWER_IO 0x00000000
-#define YUCCA_PCIX_UPPER_IO 0x0000ffff
-#define YUCCA_PCIX_LOWER_MEM 0x80000000
-#define YUCCA_PCIX_UPPER_MEM 0x8fffffff
-#define YUCCA_PCIE_LOWER_MEM 0x90000000
-#define YUCCA_PCIE_MEM_SIZE 0x10000000
-
-#define YUCCA_PCIX_MEM_SIZE 0x10000000
-#define YUCCA_PCIX_MEM_OFFSET 0x00000000
-#define YUCCA_PCIE_MEM_SIZE 0x10000000
-#define YUCCA_PCIE_MEM_OFFSET 0x00000000
-
-#endif /* __ASM_YUCCA_H__ */
-#endif /* __KERNEL__ */