diff options
Diffstat (limited to 'arch/unicore32/include/mach/regs-nand.h')
| -rw-r--r-- | arch/unicore32/include/mach/regs-nand.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/unicore32/include/mach/regs-nand.h b/arch/unicore32/include/mach/regs-nand.h index 0c33fe8c3090..a7c5563bb550 100644 --- a/arch/unicore32/include/mach/regs-nand.h +++ b/arch/unicore32/include/mach/regs-nand.h @@ -4,67 +4,67 @@ /* * ID Reg. 0 NAND_IDR0 */ -#define NAND_IDR0 __REG(PKUNITY_NAND_BASE + 0x0000) +#define NAND_IDR0 (PKUNITY_NAND_BASE + 0x0000) /* * ID Reg. 1 NAND_IDR1 */ -#define NAND_IDR1 __REG(PKUNITY_NAND_BASE + 0x0004) +#define NAND_IDR1 (PKUNITY_NAND_BASE + 0x0004) /* * ID Reg. 2 NAND_IDR2 */ -#define NAND_IDR2 __REG(PKUNITY_NAND_BASE + 0x0008) +#define NAND_IDR2 (PKUNITY_NAND_BASE + 0x0008) /* * ID Reg. 3 NAND_IDR3 */ -#define NAND_IDR3 __REG(PKUNITY_NAND_BASE + 0x000C) +#define NAND_IDR3 (PKUNITY_NAND_BASE + 0x000C) /* * Page Address Reg 0 NAND_PAR0 */ -#define NAND_PAR0 __REG(PKUNITY_NAND_BASE + 0x0010) +#define NAND_PAR0 (PKUNITY_NAND_BASE + 0x0010) /* * Page Address Reg 1 NAND_PAR1 */ -#define NAND_PAR1 __REG(PKUNITY_NAND_BASE + 0x0014) +#define NAND_PAR1 (PKUNITY_NAND_BASE + 0x0014) /* * Page Address Reg 2 NAND_PAR2 */ -#define NAND_PAR2 __REG(PKUNITY_NAND_BASE + 0x0018) +#define NAND_PAR2 (PKUNITY_NAND_BASE + 0x0018) /* * ECC Enable Reg NAND_ECCEN */ -#define NAND_ECCEN __REG(PKUNITY_NAND_BASE + 0x001C) +#define NAND_ECCEN (PKUNITY_NAND_BASE + 0x001C) /* * Buffer Reg NAND_BUF */ -#define NAND_BUF __REG(PKUNITY_NAND_BASE + 0x0020) +#define NAND_BUF (PKUNITY_NAND_BASE + 0x0020) /* * ECC Status Reg NAND_ECCSR */ -#define NAND_ECCSR __REG(PKUNITY_NAND_BASE + 0x0024) +#define NAND_ECCSR (PKUNITY_NAND_BASE + 0x0024) /* * Command Reg NAND_CMD */ -#define NAND_CMD __REG(PKUNITY_NAND_BASE + 0x0028) +#define NAND_CMD (PKUNITY_NAND_BASE + 0x0028) /* * DMA Configure Reg NAND_DMACR */ -#define NAND_DMACR __REG(PKUNITY_NAND_BASE + 0x002C) +#define NAND_DMACR (PKUNITY_NAND_BASE + 0x002C) /* * Interrupt Reg NAND_IR */ -#define NAND_IR __REG(PKUNITY_NAND_BASE + 0x0030) +#define NAND_IR (PKUNITY_NAND_BASE + 0x0030) /* * Interrupt Mask Reg NAND_IMR */ -#define NAND_IMR __REG(PKUNITY_NAND_BASE + 0x0034) +#define NAND_IMR (PKUNITY_NAND_BASE + 0x0034) /* * Chip Enable Reg NAND_CHIPEN */ -#define NAND_CHIPEN __REG(PKUNITY_NAND_BASE + 0x0038) +#define NAND_CHIPEN (PKUNITY_NAND_BASE + 0x0038) /* * Address Reg NAND_ADDR */ -#define NAND_ADDR __REG(PKUNITY_NAND_BASE + 0x003C) +#define NAND_ADDR (PKUNITY_NAND_BASE + 0x003C) /* * Command bits NAND_CMD_CMD_MASK |