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-rw-r--r--arch/mips/alchemy/devboards/db1300.c3
-rw-r--r--arch/mips/alchemy/devboards/db1550.c9
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index ef93ee3f6a2c..e476ae9472b9 100644
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -762,9 +762,10 @@ int __init db1300_dev_setup(void)
__raw_writel(PSC_SEL_CLK_SERCLK,
(void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
wmb();
- /* I2C uses internal 48MHz EXTCLK1 */
+ /* I2C driver wants 50MHz, get as close as possible */
c = clk_get(NULL, "psc3_intclk");
if (!IS_ERR(c)) {
+ clk_set_rate(c, 50000000);
clk_prepare_enable(c);
clk_put(c);
}
diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c
index 7e89936f763e..0fd5177e35ab 100644
--- a/arch/mips/alchemy/devboards/db1550.c
+++ b/arch/mips/alchemy/devboards/db1550.c
@@ -34,12 +34,9 @@ static void __init db1550_hw_setup(void)
void __iomem *base;
unsigned long v;
- /* complete SPI setup: link psc0_intclk to a 48MHz source,
- * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) as well as PSC1_SYNC
- * for AC97 on PB1550.
+ /* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
+ * as well as PSC1_SYNC for AC97 on PB1550.
*/
- v = alchemy_rdsys(AU1000_SYS_CLKSRC);
- alchemy_wrsys(v | 0x000001e0, AU1000_SYS_CLKSRC);
v = alchemy_rdsys(AU1000_SYS_PINFUNC);
alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC);
@@ -586,11 +583,13 @@ int __init db1550_dev_setup(void)
c = clk_get(NULL, "psc0_intclk");
if (!IS_ERR(c)) {
+ clk_set_rate(c, 50000000);
clk_prepare_enable(c);
clk_put(c);
}
c = clk_get(NULL, "psc2_intclk");
if (!IS_ERR(c)) {
+ clk_set_rate(c, db1550_spi_platdata.mainclk_hz);
clk_prepare_enable(c);
clk_put(c);
}