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path: root/drivers/clk/meson/g12a.c
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Diffstat (limited to 'drivers/clk/meson/g12a.c')
-rw-r--r--drivers/clk/meson/g12a.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 206fafd299ea..eda4990610c8 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -1001,6 +1001,10 @@ static struct clk_fixed_factor g12a_mpll_prediv = {
},
};
+static const struct reg_sequence g12a_mpll0_init_regs[] = {
+ { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 },
+};
+
static struct clk_regmap g12a_mpll0_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
@@ -1024,6 +1028,8 @@ static struct clk_regmap g12a_mpll0_div = {
.width = 1,
},
.lock = &meson_clk_lock,
+ .init_regs = g12a_mpll0_init_regs,
+ .init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "mpll0_div",
@@ -1047,6 +1053,10 @@ static struct clk_regmap g12a_mpll0 = {
},
};
+static const struct reg_sequence g12a_mpll1_init_regs[] = {
+ { .reg = HHI_MPLL_CNTL4, .def = 0x40000033 },
+};
+
static struct clk_regmap g12a_mpll1_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
@@ -1070,6 +1080,8 @@ static struct clk_regmap g12a_mpll1_div = {
.width = 1,
},
.lock = &meson_clk_lock,
+ .init_regs = g12a_mpll1_init_regs,
+ .init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "mpll1_div",
@@ -1093,6 +1105,10 @@ static struct clk_regmap g12a_mpll1 = {
},
};
+static const struct reg_sequence g12a_mpll2_init_regs[] = {
+ { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },
+};
+
static struct clk_regmap g12a_mpll2_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
@@ -1116,6 +1132,8 @@ static struct clk_regmap g12a_mpll2_div = {
.width = 1,
},
.lock = &meson_clk_lock,
+ .init_regs = g12a_mpll2_init_regs,
+ .init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "mpll2_div",
@@ -1139,6 +1157,10 @@ static struct clk_regmap g12a_mpll2 = {
},
};
+static const struct reg_sequence g12a_mpll3_init_regs[] = {
+ { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },
+};
+
static struct clk_regmap g12a_mpll3_div = {
.data = &(struct meson_clk_mpll_data){
.sdm = {
@@ -1162,6 +1184,8 @@ static struct clk_regmap g12a_mpll3_div = {
.width = 1,
},
.lock = &meson_clk_lock,
+ .init_regs = g12a_mpll3_init_regs,
+ .init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
},
.hw.init = &(struct clk_init_data){
.name = "mpll3_div",