diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/core_types.h | 26 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 41 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 110 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 16 |
8 files changed, 207 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h index f9363f642f92..392cff2cd558 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -30,6 +30,11 @@ struct core_dc { /* Inputs into BW and WM calculations. */ struct bw_calcs_dceip bw_dceip; struct bw_calcs_vbios bw_vbios; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_soc_bounding_box dcn_soc; + struct dcn_ip_params dcn_ip; + struct display_mode_lib dml; +#endif /* HW functions */ struct hw_sequencer_funcs hwss; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 9e5e0ba5b10b..c1273d6142c4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -28,8 +28,11 @@ #include "dc.h" #include "dce_calcs.h" +#include "dcn_calcs.h" #include "ddc_service_types.h" #include "dc_bios_types.h" +#include "mem_input.h" +#include "mpc.h" struct core_stream; @@ -254,6 +257,7 @@ struct resource_pool { struct abm *abm; struct dmcu *dmcu; + struct mpc *mpc; const struct resource_funcs *funcs; const struct resource_caps *res_cap; @@ -287,10 +291,20 @@ struct pipe_ctx { struct pipe_ctx *top_pipe; struct pipe_ctx *bottom_pipe; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + uint8_t mpc_idx; + struct _vcs_dpi_display_dlg_regs_st dlg_regs; + struct _vcs_dpi_display_ttu_regs_st ttu_regs; + struct _vcs_dpi_display_rq_regs_st rq_regs; + struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; +#endif }; struct resource_context { struct pipe_ctx pipe_ctx[MAX_PIPES]; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct mpc_tree_cfg mpc_tree[MAX_PIPES]; +#endif bool is_stream_enc_acquired[MAX_PIPES * 2]; bool is_audio_acquired[MAX_PIPES]; uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; @@ -309,6 +323,18 @@ struct validate_context { /* Note: these are big structures, do *not* put on stack! */ struct dm_pp_display_configuration pp_display_cfg; int dispclk_khz; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + int dppclk_khz; + bool dppclk_div; + int dcfclk_khz; + int dcfclk_deep_sleep_khz; + int socclk_khz; + int fclk_khz; + int dram_ccm_us; + int min_active_dram_ccm_us; + struct dcn_watermark_set watermarks; + struct dcn_bw_internal_vars dcn_bw_vars; +#endif }; #endif /* _CORE_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h index 97f26b55535f..240ab11d1d30 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h @@ -37,6 +37,13 @@ struct clocks_value { bool dispclk_notify_pplib_done; bool pixelclk_notify_pplib_done; bool phyclk_notigy_pplib_done; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + int dcfclock_in_khz; + int dppclk_in_khz; + int mclk_in_khz; + int phyclk_in_khz; + int common_vdd_level; +#endif }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index 2d472d8ef555..0f952e5b3ae8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -122,6 +122,7 @@ struct ipp_funcs { struct input_pixel_processor *ipp, const struct pwl_params *params); + void (*ipp_destroy)(struct input_pixel_processor **ipp); }; #endif /* __DAL_IPP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 179f5ad70f48..0880ce98c90c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -31,6 +31,30 @@ #include "dce/dce_mem_input.h" /* temporary */ +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dml/display_mode_structs.h" + +struct cstate_pstate_watermarks_st { + uint32_t cstate_exit_ns; + uint32_t cstate_enter_plus_exit_ns; + uint32_t pstate_change_ns; +}; + +struct dcn_watermarks { + uint32_t pte_meta_urgent_ns; + uint32_t urgent_ns; + struct cstate_pstate_watermarks_st cstate_pstate; +}; + +struct dcn_watermark_set { + struct dcn_watermarks a; + struct dcn_watermarks b; + struct dcn_watermarks c; + struct dcn_watermarks d; +}; + +#endif + struct stutter_modes { bool enhanced; bool quad_dmif_buffer; @@ -52,6 +76,23 @@ struct mem_input { }; struct mem_input_funcs { +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + void (*program_watermarks)( + struct mem_input *mem_input, + struct dcn_watermark_set *watermarks, + unsigned int refclk_period_ns); + + void (*mem_input_setup)( + struct mem_input *mem_input, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs, + struct _vcs_dpi_display_rq_regs_st *rq_regs, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + + void (*disable_request)(struct mem_input *mem_input); + +#endif + void (*mem_input_program_display_marks)( struct mem_input *mem_input, struct bw_watermarks nbp, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h new file mode 100644 index 000000000000..2e86ebe5eeda --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -0,0 +1,110 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_MPC_H__ +#define __DC_MPC_H__ + +/* define the maximum number of pipes + * MAX_NUM_PIPPES = MAX_PIPES defined in core_type.h + */ +enum { + MAX_NUM_PIPPES = 6 +}; + +enum blend_mode { + DIGI_BYPASS = 0, /* digital bypass */ + TOP_PASSTHRU, /* top layer pass through */ + TOP_BLND /* top layer blend */ +}; + +/* This structure define the mpc tree configuration + * num_pipes - number of pipes of the tree + * opp_id - instance id of OPP to drive MPC + * dpp- array of DPP index + * mpcc - array of MPCC index + * mode - the most bottom layer MPCC mode control. + * All other layers need to be program to 3 + * + * The connection will be: + * mpcc[num_pipes-1]->mpcc[num_pipes-2]->...->mpcc[1]->mpcc[0]->OPP[opp_id] + * dpp[0]->mpcc[0] + * dpp[1]->mpcc[1] + * ... + * dpp[num_pipes-1]->mpcc[num_pipes-1] + * mpcc[0] is the most top layer of MPC tree, + * mpcc[num_pipes-1] is the most bottom layer. + */ + +struct mpc_tree_cfg { + uint8_t num_pipes; + uint8_t opp_id; + /* dpp pipes for blend */ + uint8_t dpp[MAX_NUM_PIPPES]; + /* mpcc insatnces for blend */ + uint8_t mpcc[MAX_NUM_PIPPES]; + enum blend_mode mode; +}; + +struct mpcc_blnd_cfg { + /* 0- perpixel alpha, 1- perpixel alpha combined with global gain, + * 2- global alpha + */ + uint8_t alpha_mode; + uint8_t global_gain; + uint8_t global_alpha; + bool overlap_only; + bool pre_multiplied_alpha; +}; + +struct mpcc_sm_cfg { + bool enable; + /* 0-single plane, 2-row subsampling, 4-column subsampling, + * 6-checkboard subsampling + */ + uint8_t sm_mode; + bool frame_alt; /* 0- disable, 1- enable */ + bool field_alt; /* 0- disable, 1- enable */ + /* 0-no force, 2-force frame polarity from top, + * 3-force frame polarity from bottom + */ + uint8_t force_next_frame_porlarity; + /* 0-no force, 2-force field polarity from top, + * 3-force field polarity from bottom + */ + uint8_t force_next_field_polarity; +}; + +struct mpcc_vupdate_lock_cfg { + bool cfg_lock; + bool adr_lock; + bool adr_cfg_lock; + bool cur0_lock; + bool cur1_lock; +}; + +struct mpc { + struct dc_context *ctx; +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 92c99c3b9002..64d43257db96 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -27,6 +27,7 @@ #define __DAL_OPP_H__ #include "hw_shared.h" +#include "dc_hw_types.h" #include "transform.h" struct fixed31_32; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 00cdaaae455c..9f130affb31c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -91,10 +91,22 @@ enum crtc_state { CRTC_STATE_VBLANK = 0, CRTC_STATE_VACTIVE }; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +struct _dlg_otg_param { + int vstartup_start; + int vupdate_offset; + int vupdate_width; + int vready_offset; + enum signal_type signal; +}; +#endif struct timing_generator { const struct timing_generator_funcs *funcs; struct dc_bios *bp; struct dc_context *ctx; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + struct _dlg_otg_param dlg_otg_param; +#endif int inst; }; @@ -155,6 +167,10 @@ struct timing_generator_funcs { bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + void (*program_global_sync)(struct timing_generator *tg); + void (*enable_optc_clock)(struct timing_generator *tg, bool enable); +#endif }; #endif |