diff options
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a6xx_gpu.h')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 34822b080759..0fb7febf70e7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -12,6 +12,20 @@ extern bool hang_debug; +/** + * struct a6xx_info - a6xx specific information from device table + * + * @hwcg: hw clock gating register sequence + * @protect: CP_PROTECT settings + */ +struct a6xx_info { + const struct adreno_reglist *hwcg; + const struct adreno_protect *protect; + u32 gmu_chipid; + u32 gmu_cgc_mode; + u32 prim_fifo_threshold; +}; + struct a6xx_gpu { struct adreno_gpu base; @@ -69,12 +83,12 @@ static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u3 static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) { - return msm_readl(a6xx_gpu->llc_mmio + (reg << 2)); + return readl(a6xx_gpu->llc_mmio + (reg << 2)); } static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) { - msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); + writel(value, a6xx_gpu->llc_mmio + (reg << 2)); } #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ |