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path: root/drivers/pinctrl/intel/pinctrl-baytrail.c
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Diffstat (limited to 'drivers/pinctrl/intel/pinctrl-baytrail.c')
-rw-r--r--drivers/pinctrl/intel/pinctrl-baytrail.c104
1 files changed, 46 insertions, 58 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index 770a2723ef81..27aef62fc7c0 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -18,6 +18,7 @@
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/seq_file.h>
+#include <linux/string_helpers.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
@@ -52,10 +53,9 @@
#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
-#define BYT_PULL_ASSIGN_SHIFT 7
#define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
-#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
-#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
+#define BYT_PULL_ASSIGN_DOWN BIT(8)
+#define BYT_PULL_ASSIGN_UP BIT(7)
#define BYT_PIN_MUX GENMASK(2, 0)
/* BYT_VAL_REG register bits */
@@ -668,8 +668,7 @@ static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
if (!padcfg0) {
- dev_warn(vg->dev,
- "Group %s, pin %i not muxed (no padcfg0)\n",
+ dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
group.grp.name, i);
continue;
}
@@ -698,8 +697,7 @@ static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
if (!padcfg0) {
- dev_warn(vg->dev,
- "Group %s, pin %i not muxed (no padcfg0)\n",
+ dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
group.grp.name, i);
continue;
}
@@ -755,9 +753,7 @@ static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int off
value = readl(reg);
/* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
- if (value & BYT_DIRECT_IRQ_EN)
- /* nothing to do */ ;
- else
+ if (!(value & BYT_DIRECT_IRQ_EN))
value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
writel(value, reg);
@@ -791,7 +787,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
value |= gpio_mux;
writel(value, reg);
- dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
+ dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
}
raw_spin_unlock_irqrestore(&byt_lock, flags);
@@ -823,7 +819,9 @@ static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
* themselves in the foot.
*/
if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
- dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
+ dev_info_once(vg->dev,
+ "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n",
+ offset);
}
static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
@@ -1026,9 +1024,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
if (val & BYT_INPUT_EN) {
val &= ~BYT_INPUT_EN;
writel(val, val_reg);
- dev_warn(vg->dev,
- "pin %u forcibly set to input mode\n",
- offset);
+ dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
}
conf &= ~BYT_PULL_ASSIGN_MASK;
@@ -1048,9 +1044,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
if (val & BYT_INPUT_EN) {
val &= ~BYT_INPUT_EN;
writel(val, val_reg);
- dev_warn(vg->dev,
- "pin %u forcibly set to input mode\n",
- offset);
+ dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
}
conf &= ~BYT_PULL_ASSIGN_MASK;
@@ -1245,39 +1239,35 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
for (i = 0; i < vg->soc->npins; i++) {
const struct intel_community *comm;
+ void __iomem *conf_reg, *val_reg;
const char *pull_str = NULL;
const char *pull = NULL;
- void __iomem *reg;
unsigned long flags;
const char *label;
unsigned int pin;
- raw_spin_lock_irqsave(&byt_lock, flags);
pin = vg->soc->pins[i].number;
- reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
- if (!reg) {
- seq_printf(s,
- "Could not retrieve pin %i conf0 reg\n",
- pin);
- raw_spin_unlock_irqrestore(&byt_lock, flags);
+
+ conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
+ if (!conf_reg) {
+ seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin);
continue;
}
- conf0 = readl(reg);
- reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
- if (!reg) {
- seq_printf(s,
- "Could not retrieve pin %i val reg\n", pin);
- raw_spin_unlock_irqrestore(&byt_lock, flags);
+ val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
+ if (!val_reg) {
+ seq_printf(s, "Pin %i: can't retrieve VAL\n", pin);
continue;
}
- val = readl(reg);
+
+ raw_spin_lock_irqsave(&byt_lock, flags);
+ conf0 = readl(conf_reg);
+ val = readl(val_reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
comm = byt_get_community(vg, pin);
if (!comm) {
- seq_printf(s,
- "Could not get community for pin %i\n", pin);
+ seq_printf(s, "Pin %i: can't retrieve community\n", pin);
continue;
}
label = gpiochip_is_requested(chip, i);
@@ -1314,7 +1304,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
label,
val & BYT_INPUT_EN ? " " : "in",
val & BYT_OUTPUT_EN ? " " : "out",
- val & BYT_LEVEL ? "hi" : "lo",
+ str_hi_lo(val & BYT_LEVEL),
comm->pad_map[i], comm->pad_map[i] * 16,
conf0 & 0x7,
conf0 & BYT_TRIG_NEG ? " fall" : " ",
@@ -1429,7 +1419,7 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
value = readl(reg);
WARN(value & BYT_DIRECT_IRQ_EN,
- "Bad pad config for io mode, force direct_irq_en bit clearing");
+ "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing");
/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
* are used to indicate high and low level triggering
@@ -1476,9 +1466,7 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
if (!reg) {
- dev_warn(vg->dev,
- "Pin %i: could not retrieve interrupt status register\n",
- base);
+ dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
continue;
}
@@ -1501,7 +1489,7 @@ static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 c
sizeof(direct_irq_mux));
match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
if (!match) {
- dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
+ dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin);
return false;
}
@@ -1528,7 +1516,8 @@ static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 c
trig = conf0 & BYT_TRIG_MASK;
if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
- dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
+ dev_warn(vg->dev,
+ FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n",
pin, conf0);
return false;
}
@@ -1555,9 +1544,7 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip,
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
- dev_warn(vg->dev,
- "Pin %i: could not retrieve conf0 register\n",
- i);
+ dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i);
continue;
}
@@ -1588,9 +1575,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
if (!reg) {
- dev_warn(vg->dev,
- "Pin %i: could not retrieve irq status reg\n",
- base);
+ dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
continue;
}
@@ -1600,7 +1585,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
value = readl(reg);
if (value)
dev_err(vg->dev,
- "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
+ "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n",
base / 32, value);
}
@@ -1764,15 +1749,17 @@ static int byt_gpio_suspend(struct device *dev)
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
- dev_warn(vg->dev,
- "Pin %i: could not retrieve conf0 register\n",
- i);
+ dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
continue;
}
value = readl(reg) & BYT_CONF0_RESTORE_MASK;
vg->context.pads[i].conf0 = value;
reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
+ if (!reg) {
+ dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
+ continue;
+ }
value = readl(reg) & BYT_VAL_RESTORE_MASK;
vg->context.pads[i].val = value;
}
@@ -1796,9 +1783,7 @@ static int byt_gpio_resume(struct device *dev)
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
- dev_warn(vg->dev,
- "Pin %i: could not retrieve conf0 register\n",
- i);
+ dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
continue;
}
value = readl(reg);
@@ -1807,10 +1792,14 @@ static int byt_gpio_resume(struct device *dev)
value &= ~BYT_CONF0_RESTORE_MASK;
value |= vg->context.pads[i].conf0;
writel(value, reg);
- dev_info(dev, "restored pin %d conf0 %#08x", i, value);
+ dev_info(dev, "restored pin %d CONF0 %#08x", i, value);
}
reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
+ if (!reg) {
+ dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
+ continue;
+ }
value = readl(reg);
if ((value & BYT_VAL_RESTORE_MASK) !=
vg->context.pads[i].val) {
@@ -1820,8 +1809,7 @@ static int byt_gpio_resume(struct device *dev)
v |= vg->context.pads[i].val;
if (v != value) {
writel(v, reg);
- dev_dbg(dev, "restored pin %d val %#08x\n",
- i, v);
+ dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v);
}
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-08 19:43:36 +0000