diff options
Diffstat (limited to 'drivers/staging/mt7621-dts/mt7621.dtsi')
| -rw-r--r-- | drivers/staging/mt7621-dts/mt7621.dtsi | 75 |
1 files changed, 40 insertions, 35 deletions
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 093a7f8091b5..eeabe9c0f4fb 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -55,7 +55,7 @@ #address-cells = <1>; #size-cells = <1>; - sysc: sysc@0 { + sysc: syscon@0 { compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; @@ -122,7 +122,7 @@ status = "disabled"; }; - memc: memc@5000 { + memc: syscon@5000 { compatible = "mediatek,mt7621-memc", "syscon"; reg = <0x5000 0x1000>; }; @@ -372,13 +372,6 @@ clock-names = "nand"; }; - ethsys: syscon@1e000000 { - compatible = "mediatek,mt7621-ethsys", - "syscon"; - reg = <0x1e000000 0x1000>; - #clock-cells = <1>; - }; - ethernet: ethernet@1e100000 { compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; @@ -396,7 +389,7 @@ interrupt-parent = <&gic>; interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; - mediatek,ethsys = <ðsys>; + mediatek,ethsys = <&sysc>; gmac0: mac@0 { @@ -488,10 +481,10 @@ pcie: pcie@1e140000 { compatible = "mediatek,mt7621-pci"; - reg = <0x1e140000 0x100 /* host-pci bridge registers */ - 0x1e142000 0x100 /* pcie port 0 RC control registers */ - 0x1e143000 0x100 /* pcie port 1 RC control registers */ - 0x1e144000 0x100>; /* pcie port 2 RC control registers */ + reg = <0x1e140000 0x100>, /* host-pci bridge registers */ + <0x1e142000 0x100>, /* pcie port 0 RC control registers */ + <0x1e143000 0x100>, /* pcie port 1 RC control registers */ + <0x1e144000 0x100>; /* pcie port 2 RC control registers */ #address-cells = <3>; #size-cells = <2>; @@ -500,64 +493,76 @@ device_type = "pci"; - bus-range = <0 255>; - ranges = < - 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ - 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ - >; + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ + <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH - GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH - GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xF800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; - reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&sysc MT7621_CLK_PCIE0>, - <&sysc MT7621_CLK_PCIE1>, - <&sysc MT7621_CLK_PCIE2>; - clock-names = "pcie0", "pcie1", "pcie2"; - phys = <&pcie0_phy 1>, <&pcie2_phy 0>; - phy-names = "pcie-phy0", "pcie-phy2"; - reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; pcie@0,0 { reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 24>; + clocks = <&sysc MT7621_CLK_PCIE0>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy0"; ranges; - bus-range = <0x00 0xff>; }; pcie@1,0 { reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 25>; + clocks = <&sysc MT7621_CLK_PCIE1>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy1"; ranges; - bus-range = <0x00 0xff>; }; pcie@2,0 { reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 26>; + clocks = <&sysc MT7621_CLK_PCIE2>; + phys = <&pcie2_phy 0>; + phy-names = "pcie-phy2"; ranges; - bus-range = <0x00 0xff>; }; }; pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; #phy-cells = <1>; }; pcie2_phy: pcie-phy@1e14a000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e14a000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; #phy-cells = <1>; }; }; |