diff options
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,qdu1000-rpmh.h | 98 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h | 231 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sc7180.h | 3 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sc8180x.h | 3 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sc8280xp.h | 4 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sdm670-rpmh.h | 136 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sdx55.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sm8150.h | 3 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sm8250.h | 3 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sm8550-rpmh.h | 189 |
10 files changed, 656 insertions, 16 deletions
diff --git a/include/dt-bindings/interconnect/qcom,qdu1000-rpmh.h b/include/dt-bindings/interconnect/qcom,qdu1000-rpmh.h new file mode 100644 index 000000000000..7f0ad1571128 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,qdu1000-rpmh.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QDU1000_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_QDU1000_H + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define SLAVE_QUP_CORE_0 2 +#define SLAVE_QUP_CORE_1 3 + +#define MASTER_SYS_TCU 0 +#define MASTER_APPSS_PROC 1 +#define MASTER_GEMNOC_ECPRI_DMA 2 +#define MASTER_FEC_2_GEMNOC 3 +#define MASTER_ANOC_PCIE_GEM_NOC 4 +#define MASTER_SNOC_GC_MEM_NOC 5 +#define MASTER_SNOC_SF_MEM_NOC 6 +#define MASTER_MSS_PROC 7 +#define SLAVE_GEM_NOC_CNOC 8 +#define SLAVE_LLCC 9 +#define SLAVE_GEMNOC_MODEM_CNOC 10 +#define SLAVE_MEM_NOC_PCIE_SNOC 11 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_GIC_AHB 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QPIC 2 +#define MASTER_QSPI_0 3 +#define MASTER_QUP_0 4 +#define MASTER_QUP_1 5 +#define MASTER_SNOC_CFG 6 +#define MASTER_ANOC_SNOC 7 +#define MASTER_ANOC_GSI 8 +#define MASTER_GEM_NOC_CNOC 9 +#define MASTER_GEMNOC_MODEM_CNOC 10 +#define MASTER_GEM_NOC_PCIE_SNOC 11 +#define MASTER_CRYPTO 12 +#define MASTER_ECPRI_GSI 13 +#define MASTER_PIMEM 14 +#define MASTER_SNOC_ECPRI_DMA 15 +#define MASTER_GIC 16 +#define MASTER_PCIE 17 +#define MASTER_QDSS_ETR 18 +#define MASTER_QDSS_ETR_1 19 +#define MASTER_SDCC_1 20 +#define MASTER_USB3 21 +#define SLAVE_AHB2PHY_SOUTH 22 +#define SLAVE_AHB2PHY_NORTH 23 +#define SLAVE_AHB2PHY_EAST 24 +#define SLAVE_AOSS 25 +#define SLAVE_CLK_CTL 26 +#define SLAVE_RBCPR_CX_CFG 27 +#define SLAVE_RBCPR_MX_CFG 28 +#define SLAVE_CRYPTO_0_CFG 29 +#define SLAVE_ECPRI_CFG 30 +#define SLAVE_IMEM_CFG 31 +#define SLAVE_IPC_ROUTER_CFG 32 +#define SLAVE_CNOC_MSS 33 +#define SLAVE_PCIE_CFG 34 +#define SLAVE_PDM 35 +#define SLAVE_PIMEM_CFG 36 +#define SLAVE_PRNG 37 +#define SLAVE_QDSS_CFG 38 +#define SLAVE_QPIC 40 +#define SLAVE_QSPI_0 41 +#define SLAVE_QUP_0 42 +#define SLAVE_QUP_1 43 +#define SLAVE_SDCC_2 44 +#define SLAVE_SMBUS_CFG 45 +#define SLAVE_SNOC_CFG 46 +#define SLAVE_TCSR 47 +#define SLAVE_TLMM 48 +#define SLAVE_TME_CFG 49 +#define SLAVE_TSC_CFG 50 +#define SLAVE_USB3_0 51 +#define SLAVE_VSENSE_CTRL_CFG 52 +#define SLAVE_A1NOC_SNOC 53 +#define SLAVE_ANOC_SNOC_GSI 54 +#define SLAVE_DDRSS_CFG 55 +#define SLAVE_ECPRI_GEMNOC 56 +#define SLAVE_SNOC_GEM_NOC_GC 57 +#define SLAVE_SNOC_GEM_NOC_SF 58 +#define SLAVE_MODEM_OFFLINE 59 +#define SLAVE_ANOC_PCIE_GEM_NOC 60 +#define SLAVE_IMEM 61 +#define SLAVE_PIMEM 62 +#define SLAVE_SERVICE_SNOC 63 +#define SLAVE_ETHERNET_SS 64 +#define SLAVE_PCIE_0 65 +#define SLAVE_QDSS_STM 66 +#define SLAVE_TCU 67 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h b/include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h new file mode 100644 index 000000000000..f21c39d0928e --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H + +/* aggre1_noc */ +#define MASTER_QUP_3 0 +#define MASTER_EMAC 1 +#define MASTER_EMAC_1 2 +#define MASTER_SDC 3 +#define MASTER_UFS_MEM 4 +#define MASTER_USB2 5 +#define MASTER_USB3_0 6 +#define MASTER_USB3_1 7 +#define SLAVE_A1NOC_SNOC 8 + +/* aggre2_noc */ +#define MASTER_QDSS_BAM 0 +#define MASTER_QUP_0 1 +#define MASTER_QUP_1 2 +#define MASTER_QUP_2 3 +#define MASTER_CNOC_A2NOC 4 +#define MASTER_CRYPTO_CORE0 5 +#define MASTER_CRYPTO_CORE1 6 +#define MASTER_IPA 7 +#define MASTER_QDSS_ETR_0 8 +#define MASTER_QDSS_ETR_1 9 +#define MASTER_UFS_CARD 10 +#define SLAVE_A2NOC_SNOC 11 + +/* clk_virt */ +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define MASTER_QUP_CORE_3 3 +#define SLAVE_QUP_CORE_0 4 +#define SLAVE_QUP_CORE_1 5 +#define SLAVE_QUP_CORE_2 6 +#define SLAVE_QUP_CORE_3 7 + +/* config_noc */ +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AHB2PHY_0 2 +#define SLAVE_AHB2PHY_1 3 +#define SLAVE_AHB2PHY_2 4 +#define SLAVE_AHB2PHY_3 5 +#define SLAVE_ANOC_THROTTLE_CFG 6 +#define SLAVE_AOSS 7 +#define SLAVE_APPSS 8 +#define SLAVE_BOOT_ROM 9 +#define SLAVE_CAMERA_CFG 10 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 12 +#define SLAVE_CLK_CTL 13 +#define SLAVE_CDSP_CFG 14 +#define SLAVE_CDSP1_CFG 15 +#define SLAVE_RBCPR_CX_CFG 16 +#define SLAVE_RBCPR_MMCX_CFG 17 +#define SLAVE_RBCPR_MX_CFG 18 +#define SLAVE_CPR_NSPCX 19 +#define SLAVE_CRYPTO_0_CFG 20 +#define SLAVE_CX_RDPM 21 +#define SLAVE_DISPLAY_CFG 22 +#define SLAVE_DISPLAY_RT_THROTTLE_CFG 23 +#define SLAVE_DISPLAY1_CFG 24 +#define SLAVE_DISPLAY1_RT_THROTTLE_CFG 25 +#define SLAVE_EMAC_CFG 26 +#define SLAVE_EMAC1_CFG 27 +#define SLAVE_GP_DSP0_CFG 28 +#define SLAVE_GP_DSP1_CFG 29 +#define SLAVE_GPDSP0_THROTTLE_CFG 30 +#define SLAVE_GPDSP1_THROTTLE_CFG 31 +#define SLAVE_GPU_TCU_THROTTLE_CFG 32 +#define SLAVE_GFX3D_CFG 33 +#define SLAVE_HWKM 34 +#define SLAVE_IMEM_CFG 35 +#define SLAVE_IPA_CFG 36 +#define SLAVE_IPC_ROUTER_CFG 37 +#define SLAVE_LPASS 38 +#define SLAVE_LPASS_THROTTLE_CFG 39 +#define SLAVE_MX_RDPM 40 +#define SLAVE_MXC_RDPM 41 +#define SLAVE_PCIE_0_CFG 42 +#define SLAVE_PCIE_1_CFG 43 +#define SLAVE_PCIE_RSC_CFG 44 +#define SLAVE_PCIE_TCU_THROTTLE_CFG 45 +#define SLAVE_PCIE_THROTTLE_CFG 46 +#define SLAVE_PDM 47 +#define SLAVE_PIMEM_CFG 48 +#define SLAVE_PKA_WRAPPER_CFG 49 +#define SLAVE_QDSS_CFG 50 +#define SLAVE_QM_CFG 51 +#define SLAVE_QM_MPU_CFG 52 +#define SLAVE_QUP_0 53 +#define SLAVE_QUP_1 54 +#define SLAVE_QUP_2 55 +#define SLAVE_QUP_3 56 +#define SLAVE_SAIL_THROTTLE_CFG 57 +#define SLAVE_SDC1 58 +#define SLAVE_SECURITY 59 +#define SLAVE_SNOC_THROTTLE_CFG 60 +#define SLAVE_TCSR 61 +#define SLAVE_TLMM 62 +#define SLAVE_TSC_CFG 63 +#define SLAVE_UFS_CARD_CFG 64 +#define SLAVE_UFS_MEM_CFG 65 +#define SLAVE_USB2 66 +#define SLAVE_USB3_0 67 +#define SLAVE_USB3_1 68 +#define SLAVE_VENUS_CFG 69 +#define SLAVE_VENUS_CVP_THROTTLE_CFG 70 +#define SLAVE_VENUS_V_CPU_THROTTLE_CFG 71 +#define SLAVE_VENUS_VCODEC_THROTTLE_CFG 72 +#define SLAVE_DDRSS_CFG 73 +#define SLAVE_GPDSP_NOC_CFG 74 +#define SLAVE_CNOC_MNOC_HF_CFG 75 +#define SLAVE_CNOC_MNOC_SF_CFG 76 +#define SLAVE_PCIE_ANOC_CFG 77 +#define SLAVE_SNOC_CFG 78 +#define SLAVE_BOOT_IMEM 79 +#define SLAVE_IMEM 80 +#define SLAVE_PIMEM 81 +#define SLAVE_PCIE_0 82 +#define SLAVE_PCIE_1 83 +#define SLAVE_QDSS_STM 84 +#define SLAVE_TCU 85 + +/* dc_noc */ +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_GEM_NOC_CFG 2 + +/* gem_noc */ +#define MASTER_GPU_TCU 0 +#define MASTER_PCIE_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_APPSS_PROC 3 +#define MASTER_COMPUTE_NOC 4 +#define MASTER_COMPUTE_NOC_1 5 +#define MASTER_GEM_NOC_CFG 6 +#define MASTER_GPDSP_SAIL 7 +#define MASTER_GFX3D 8 +#define MASTER_MNOC_HF_MEM_NOC 9 +#define MASTER_MNOC_SF_MEM_NOC 10 +#define MASTER_ANOC_PCIE_GEM_NOC 11 +#define MASTER_SNOC_GC_MEM_NOC 12 +#define MASTER_SNOC_SF_MEM_NOC 13 +#define SLAVE_GEM_NOC_CNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_GEM_NOC_PCIE_CNOC 16 +#define SLAVE_SERVICE_GEM_NOC_1 17 +#define SLAVE_SERVICE_GEM_NOC_2 18 +#define SLAVE_SERVICE_GEM_NOC 19 +#define SLAVE_SERVICE_GEM_NOC2 20 + +/* gpdsp_anoc */ +#define MASTER_DSP0 0 +#define MASTER_DSP1 1 +#define SLAVE_GP_DSP_SAIL_NOC 2 + +/* lpass_ag_noc */ +#define MASTER_CNOC_LPASS_AG_NOC 0 +#define MASTER_LPASS_PROC 1 +#define SLAVE_LPASS_CORE_CFG 2 +#define SLAVE_LPASS_LPI_CFG 3 +#define SLAVE_LPASS_MPU_CFG 4 +#define SLAVE_LPASS_TOP_CFG 5 +#define SLAVE_LPASS_SNOC 6 +#define SLAVE_SERVICES_LPASS_AML_NOC 7 +#define SLAVE_SERVICE_LPASS_AG_NOC 8 + +/* mc_virt */ +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +/*mmss_noc */ +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_ICP 1 +#define MASTER_CAMNOC_SF 2 +#define MASTER_MDP0 3 +#define MASTER_MDP1 4 +#define MASTER_MDP_CORE1_0 5 +#define MASTER_MDP_CORE1_1 6 +#define MASTER_CNOC_MNOC_HF_CFG 7 +#define MASTER_CNOC_MNOC_SF_CFG 8 +#define MASTER_VIDEO_P0 9 +#define MASTER_VIDEO_P1 10 +#define MASTER_VIDEO_PROC 11 +#define MASTER_VIDEO_V_PROC 12 +#define SLAVE_MNOC_HF_MEM_NOC 13 +#define SLAVE_MNOC_SF_MEM_NOC 14 +#define SLAVE_SERVICE_MNOC_HF 15 +#define SLAVE_SERVICE_MNOC_SF 16 + +/* nspa_noc */ +#define MASTER_CDSP_NOC_CFG 0 +#define MASTER_CDSP_PROC 1 +#define SLAVE_HCP_A 2 +#define SLAVE_CDSP_MEM_NOC 3 +#define SLAVE_SERVICE_NSP_NOC 4 + +/* nspb_noc */ +#define MASTER_CDSPB_NOC_CFG 0 +#define MASTER_CDSP_PROC_B 1 +#define SLAVE_CDSPB_MEM_NOC 2 +#define SLAVE_HCP_B 3 +#define SLAVE_SERVICE_NSPB_NOC 4 + +/* pcie_anoc */ +#define MASTER_PCIE_0 0 +#define MASTER_PCIE_1 1 +#define SLAVE_ANOC_PCIE_GEM_NOC 2 + +/* system_noc */ +#define MASTER_GIC_AHB 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_LPASS_ANOC 3 +#define MASTER_SNOC_CFG 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_SNOC_GEM_NOC_GC 7 +#define SLAVE_SNOC_GEM_NOC_SF 8 +#define SLAVE_SERVICE_SNOC 9 + +#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H */ diff --git a/include/dt-bindings/interconnect/qcom,sc7180.h b/include/dt-bindings/interconnect/qcom,sc7180.h index f9970f6032eb..de5d5867bd67 100644 --- a/include/dt-bindings/interconnect/qcom,sc7180.h +++ b/include/dt-bindings/interconnect/qcom,sc7180.h @@ -108,9 +108,6 @@ #define SLAVE_LLCC 11 #define SLAVE_SERVICE_GEM_NOC 12 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI1 1 diff --git a/include/dt-bindings/interconnect/qcom,sc8180x.h b/include/dt-bindings/interconnect/qcom,sc8180x.h index e84cfec5afdd..0bdc8d6cb401 100644 --- a/include/dt-bindings/interconnect/qcom,sc8180x.h +++ b/include/dt-bindings/interconnect/qcom,sc8180x.h @@ -129,9 +129,6 @@ #define SLAVE_SERVICE_GEM_NOC 16 #define SLAVE_SERVICE_GEM_NOC_1 17 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI_CH0 1 diff --git a/include/dt-bindings/interconnect/qcom,sc8280xp.h b/include/dt-bindings/interconnect/qcom,sc8280xp.h index a3e5fda7c127..f89f47e99c6d 100644 --- a/include/dt-bindings/interconnect/qcom,sc8280xp.h +++ b/include/dt-bindings/interconnect/qcom,sc8280xp.h @@ -48,11 +48,11 @@ #define SLAVE_SERVICE_A2NOC 19 /* clk_virt */ -#define MASTER_IPA_CORE 0 +/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */ #define MASTER_QUP_CORE_0 1 #define MASTER_QUP_CORE_1 2 #define MASTER_QUP_CORE_2 3 -#define SLAVE_IPA_CORE 4 +/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SLAVE_QUP_CORE_0 5 #define SLAVE_QUP_CORE_1 6 #define SLAVE_QUP_CORE_2 7 diff --git a/include/dt-bindings/interconnect/qcom,sdm670-rpmh.h b/include/dt-bindings/interconnect/qcom,sdm670-rpmh.h new file mode 100644 index 000000000000..9b516cc360bb --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sdm670-rpmh.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Qualcomm SDM670 interconnect IDs + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_BLSP_1 1 +#define MASTER_TSIF 2 +#define MASTER_EMMC 3 +#define MASTER_SDCC_2 4 +#define MASTER_SDCC_4 5 +#define MASTER_UFS_MEM 6 +#define SLAVE_A1NOC_SNOC 7 +#define SLAVE_SERVICE_A1NOC 8 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_BLSP_2 2 +#define MASTER_CNOC_A2NOC 3 +#define MASTER_CRYPTO_CORE_0 4 +#define MASTER_IPA 5 +#define MASTER_QDSS_ETR 6 +#define MASTER_USB3 7 +#define SLAVE_A2NOC_SNOC 8 +#define SLAVE_SERVICE_A2NOC 9 + + +#define MASTER_SPDM 0 +#define MASTER_SNOC_CNOC 1 +#define SLAVE_A1NOC_CFG 2 +#define SLAVE_A2NOC_CFG 3 +#define SLAVE_AOP 4 +#define SLAVE_AOSS 5 +#define SLAVE_CAMERA_CFG 6 +#define SLAVE_CLK_CTL 7 +#define SLAVE_CDSP_CFG 8 +#define SLAVE_RBCPR_CX_CFG 9 +#define SLAVE_CRYPTO_0_CFG 10 +#define SLAVE_DCC_CFG 11 +#define SLAVE_CNOC_DDRSS 12 +#define SLAVE_DISPLAY_CFG 13 +#define SLAVE_EMMC_CFG 14 +#define SLAVE_GLM 15 +#define SLAVE_GRAPHICS_3D_CFG 16 +#define SLAVE_IMEM_CFG 17 +#define SLAVE_IPA_CFG 18 +#define SLAVE_CNOC_MNOC_CFG 19 +#define SLAVE_PDM 20 +#define SLAVE_SOUTH_PHY_CFG 21 +#define SLAVE_PIMEM_CFG 22 +#define SLAVE_PRNG 23 +#define SLAVE_QDSS_CFG 24 +#define SLAVE_BLSP_2 25 +#define SLAVE_BLSP_1 26 +#define SLAVE_SDCC_2 27 +#define SLAVE_SDCC_4 28 +#define SLAVE_SNOC_CFG 29 +#define SLAVE_SPDM_WRAPPER 30 +#define SLAVE_TCSR 31 +#define SLAVE_TLMM_NORTH 32 +#define SLAVE_TLMM_SOUTH 33 +#define SLAVE_TSIF 34 +#define SLAVE_UFS_MEM_CFG 35 +#define SLAVE_USB3 36 +#define SLAVE_VENUS_CFG 37 +#define SLAVE_VSENSE_CTRL_CFG 38 +#define SLAVE_CNOC_A2NOC 39 +#define SLAVE_SERVICE_CNOC 40 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_MEM_NOC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_GNOC_CFG 1 +#define SLAVE_GNOC_SNOC 2 +#define SLAVE_GNOC_MEM_NOC 3 +#define SLAVE_SERVICE_GNOC 4 + +#define MASTER_TCU_0 0 +#define MASTER_MEM_NOC_CFG 1 +#define MASTER_GNOC_MEM_NOC 2 +#define MASTER_MNOC_HF_MEM_NOC 3 +#define MASTER_MNOC_SF_MEM_NOC 4 +#define MASTER_SNOC_GC_MEM_NOC 5 +#define MASTER_SNOC_SF_MEM_NOC 6 +#define MASTER_GRAPHICS_3D 7 +#define SLAVE_MSS_PROC_MS_MPU_CFG 8 +#define SLAVE_MEM_NOC_GNOC 9 +#define SLAVE_LLCC 10 +#define SLAVE_MEM_NOC_SNOC 11 +#define SLAVE_SERVICE_MEM_NOC 12 +#define MASTER_LLCC 13 +#define SLAVE_EBI_CH0 14 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP_PORT0 4 +#define MASTER_MDP_PORT1 5 +#define MASTER_ROTATOR 6 +#define MASTER_VIDEO_P0 7 +#define MASTER_VIDEO_P1 8 +#define MASTER_VIDEO_PROC 9 +#define SLAVE_MNOC_SF_MEM_NOC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 + +#define MASTER_SNOC_CFG 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_GNOC_SNOC 3 +#define MASTER_MEM_NOC_SNOC 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_APPSS 7 +#define SLAVE_SNOC_CNOC 8 +#define SLAVE_SNOC_MEM_NOC_GC 9 +#define SLAVE_SNOC_MEM_NOC_SF 10 +#define SLAVE_OCIMEM 11 +#define SLAVE_PIMEM 12 +#define SLAVE_SERVICE_SNOC 13 +#define SLAVE_QDSS_STM 14 +#define SLAVE_TCU 15 +#define MASTER_CAMNOC_HF0_UNCOMP 16 +#define MASTER_CAMNOC_HF1_UNCOMP 17 +#define MASTER_CAMNOC_SF_UNCOMP 18 +#define SLAVE_CAMNOC_UNCOMP 19 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sdx55.h b/include/dt-bindings/interconnect/qcom,sdx55.h index bfb6524a2d90..1925f0784ab2 100644 --- a/include/dt-bindings/interconnect/qcom,sdx55.h +++ b/include/dt-bindings/interconnect/qcom,sdx55.h @@ -70,7 +70,5 @@ #define SLAVE_QDSS_STM 48 #define SLAVE_TCU 49 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 #endif diff --git a/include/dt-bindings/interconnect/qcom,sm8150.h b/include/dt-bindings/interconnect/qcom,sm8150.h index a25684680c42..ef292791f52e 100644 --- a/include/dt-bindings/interconnect/qcom,sm8150.h +++ b/include/dt-bindings/interconnect/qcom,sm8150.h @@ -121,9 +121,6 @@ #define SLAVE_LLCC 15 #define SLAVE_SERVICE_GEM_NOC 16 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI_CH0 1 diff --git a/include/dt-bindings/interconnect/qcom,sm8250.h b/include/dt-bindings/interconnect/qcom,sm8250.h index 1b4d9fbe888d..a4af5cc19271 100644 --- a/include/dt-bindings/interconnect/qcom,sm8250.h +++ b/include/dt-bindings/interconnect/qcom,sm8250.h @@ -115,9 +115,6 @@ #define SLAVE_SERVICE_GEM_NOC_2 15 #define SLAVE_SERVICE_GEM_NOC 16 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI_CH0 1 diff --git a/include/dt-bindings/interconnect/qcom,sm8550-rpmh.h b/include/dt-bindings/interconnect/qcom,sm8550-rpmh.h new file mode 100644 index 000000000000..b38d0da7886f --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm8550-rpmh.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8550_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8550_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_1 1 +#define MASTER_SDCC_4 2 +#define MASTER_UFS_MEM 3 +#define MASTER_USB3_0 4 +#define SLAVE_A1NOC_SNOC 5 + +#define MASTER_QDSS_BAM 0 +#define MASTER_QUP_2 1 +#define MASTER_CRYPTO 2 +#define MASTER_IPA 3 +#define MASTER_SP 4 +#define MASTER_QDSS_ETR 5 +#define MASTER_QDSS_ETR_1 6 +#define MASTER_SDCC_2 7 +#define SLAVE_A2NOC_SNOC 8 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define SLAVE_QUP_CORE_0 3 +#define SLAVE_QUP_CORE_1 4 +#define SLAVE_QUP_CORE_2 5 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_AHB2PHY_SOUTH 1 +#define SLAVE_AHB2PHY_NORTH 2 +#define SLAVE_APPSS 3 +#define SLAVE_CAMERA_CFG 4 +#define SLAVE_CLK_CTL 5 +#define SLAVE_RBCPR_CX_CFG 6 +#define SLAVE_RBCPR_MMCX_CFG 7 +#define SLAVE_RBCPR_MXA_CFG 8 +#define SLAVE_RBCPR_MXC_CFG 9 +#define SLAVE_CPR_NSPCX 10 +#define SLAVE_CRYPTO_0_CFG 11 +#define SLAVE_CX_RDPM 12 +#define SLAVE_DISPLAY_CFG 13 +#define SLAVE_GFX3D_CFG 14 +#define SLAVE_I2C 15 +#define SLAVE_IMEM_CFG 16 +#define SLAVE_IPA_CFG 17 +#define SLAVE_IPC_ROUTER_CFG 18 +#define SLAVE_CNOC_MSS 19 +#define SLAVE_MX_RDPM 20 +#define SLAVE_PCIE_0_CFG 21 +#define SLAVE_PCIE_1_CFG 22 +#define SLAVE_PDM 23 +#define SLAVE_PIMEM_CFG 24 +#define SLAVE_PRNG 25 +#define SLAVE_QDSS_CFG 26 +#define SLAVE_QSPI_0 27 +#define SLAVE_QUP_1 28 +#define SLAVE_QUP_2 29 +#define SLAVE_SDCC_2 30 +#define SLAVE_SDCC_4 31 +#define SLAVE_SPSS_CFG 32 +#define SLAVE_TCSR 33 +#define SLAVE_TLMM 34 +#define SLAVE_UFS_MEM_CFG 35 +#define SLAVE_USB3_0 36 +#define SLAVE_VENUS_CFG 37 +#define SLAVE_VSENSE_CTRL_CFG 38 +#define SLAVE_LPASS_QTB_CFG 39 +#define SLAVE_CNOC_MNOC_CFG 40 +#define SLAVE_NSP_QTB_CFG 41 +#define SLAVE_PCIE_ANOC_CFG 42 +#define SLAVE_QDSS_STM 43 +#define SLAVE_TCU 44 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_TME_CFG 3 +#define SLAVE_CNOC_CFG 4 +#define SLAVE_DDRSS_CFG 5 +#define SLAVE_BOOT_IMEM 6 +#define SLAVE_IMEM 7 +#define SLAVE_PCIE_0 8 +#define SLAVE_PCIE_1 9 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_GFX3D 3 +#define MASTER_LPASS_GEM_NOC 4 +#define MASTER_MSS_PROC 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_COMPUTE_NOC 8 +#define MASTER_ANOC_PCIE_GEM_NOC 9 +#define MASTER_SNOC_GC_MEM_NOC 10 +#define MASTER_SNOC_SF_MEM_NOC 11 +#define SLAVE_GEM_NOC_CNOC 12 +#define SLAVE_LLCC 13 +#define SLAVE_MEM_NOC_PCIE_SNOC 14 +#define MASTER_MNOC_HF_MEM_NOC_DISP 15 +#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16 +#define SLAVE_LLCC_DISP 17 +#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 18 +#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 19 +#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 20 +#define SLAVE_LLCC_CAM_IFE_0 21 +#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 22 +#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 23 +#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 24 +#define SLAVE_LLCC_CAM_IFE_1 25 +#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 26 +#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 27 +#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 28 +#define SLAVE_LLCC_CAM_IFE_2 29 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 +#define MASTER_LLCC_DISP 2 +#define SLAVE_EBI1_DISP 3 +#define MASTER_LLCC_CAM_IFE_0 4 +#define SLAVE_EBI1_CAM_IFE_0 5 +#define MASTER_LLCC_CAM_IFE_1 6 +#define SLAVE_EBI1_CAM_IFE_1 7 +#define MASTER_LLCC_CAM_IFE_2 8 +#define SLAVE_EBI1_CAM_IFE_2 9 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_ICP 1 +#define MASTER_CAMNOC_SF 2 +#define MASTER_MDP 3 +#define MASTER_CDSP_HCP 4 +#define MASTER_VIDEO 5 +#define MASTER_VIDEO_CV_PROC 6 +#define MASTER_VIDEO_PROC 7 +#define MASTER_VIDEO_V_PROC 8 +#define MASTER_CNOC_MNOC_CFG 9 +#define SLAVE_MNOC_HF_MEM_NOC 10 +#define SLAVE_MNOC_SF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 +#define MASTER_MDP_DISP 13 +#define SLAVE_MNOC_HF_MEM_NOC_DISP 14 +#define MASTER_CAMNOC_HF_CAM_IFE_0 15 +#define MASTER_CAMNOC_ICP_CAM_IFE_0 16 +#define MASTER_CAMNOC_SF_CAM_IFE_0 17 +#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 18 +#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 19 +#define MASTER_CAMNOC_HF_CAM_IFE_1 20 +#define MASTER_CAMNOC_ICP_CAM_IFE_1 21 +#define MASTER_CAMNOC_SF_CAM_IFE_1 22 +#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 23 +#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 24 +#define MASTER_CAMNOC_HF_CAM_IFE_2 25 +#define MASTER_CAMNOC_ICP_CAM_IFE_2 26 +#define MASTER_CAMNOC_SF_CAM_IFE_2 27 +#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 28 +#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 29 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define SLAVE_ANOC_PCIE_GEM_NOC 3 +#define SLAVE_SERVICE_PCIE_ANOC 4 + +#define MASTER_GIC_AHB 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_GIC 3 +#define SLAVE_SNOC_GEM_NOC_GC 4 +#define SLAVE_SNOC_GEM_NOC_SF 5 + +#endif |