diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/broadwellx/cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/broadwellx/cache.json | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json index 6a134928b3f0..781e7c64e71f 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -16,7 +16,7 @@ "UMask": "0x2" }, { - "BriefDescription": "L1D miss oustandings duration in cycles", + "BriefDescription": "L1D miss outstandings duration in cycles", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", @@ -454,22 +454,22 @@ "UMask": "0x20" }, { - "BriefDescription": "All retired load uops.", + "BriefDescription": "Retired load uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store uops.", + "BriefDescription": "Retired store uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", - "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "PublicDescription": "Counts all retired store uops.", "SampleAfterValue": "2000003", "UMask": "0x82" }, @@ -541,10 +541,10 @@ "UMask": "0x80" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests", + "BriefDescription": "Cacheable and non-cacheable code read requests", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "PublicDescription": "This event counts both cacheable and non-cacheable code read requests.", "SampleAfterValue": "100003", "UMask": "0x2" }, |