diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json | 437 |
1 files changed, 401 insertions, 36 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json index dd1b95655d1d..3ffb70ff573d 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json @@ -1,91 +1,456 @@ [ { - "BriefDescription": "PCU clock ticks. Use to get percentages of PCU cycles events", + "BriefDescription": "pclk Cycles", "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", - "Filter": "occ_sel=1", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c0 %", + "EventCode": "0x60", + "EventName": "UNC_P_CORE0_TRANSITION_CYCLES", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the number of cores that are in C3. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", - "Filter": "occ_sel=2", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c3 %", + "EventCode": "0x6A", + "EventName": "UNC_P_CORE10_TRANSITION_CYCLES", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "This is an occupancy event that tracks the number of cores that are in C6. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events ", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", - "Filter": "occ_sel=3", - "MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "power_state_occupancy.cores_c6 %", + "EventCode": "0x6B", + "EventName": "UNC_P_CORE11_TRANSITION_CYCLES", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip", + "BriefDescription": "Core C State Transition Cycles", "Counter": "0,1,2,3", - "EventCode": "0xA", - "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", - "MetricExpr": "(UNC_P_PROCHOT_EXTERNAL_CYCLES / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "prochot_external_cycles %", + "EventCode": "0x6C", + "EventName": "UNC_P_CORE12_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x6D", + "EventName": "UNC_P_CORE13_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x6E", + "EventName": "UNC_P_CORE14_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x6F", + "EventName": "UNC_P_CORE15_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x70", + "EventName": "UNC_P_CORE16_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "UNC_P_CORE17_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "UNC_P_CORE1_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x62", + "EventName": "UNC_P_CORE2_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "UNC_P_CORE3_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x64", + "EventName": "UNC_P_CORE4_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x65", + "EventName": "UNC_P_CORE5_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x66", + "EventName": "UNC_P_CORE6_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x67", + "EventName": "UNC_P_CORE7_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x68", + "EventName": "UNC_P_CORE8_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_P_CORE9_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_P_DEMOTIONS_CORE0", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x31", + "EventName": "UNC_P_DEMOTIONS_CORE1", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3A", + "EventName": "UNC_P_DEMOTIONS_CORE10", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3B", + "EventName": "UNC_P_DEMOTIONS_CORE11", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "UNC_P_DEMOTIONS_CORE12", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3D", + "EventName": "UNC_P_DEMOTIONS_CORE13", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3E", + "EventName": "UNC_P_DEMOTIONS_CORE14", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x3F", + "EventName": "UNC_P_DEMOTIONS_CORE15", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_P_DEMOTIONS_CORE16", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_P_DEMOTIONS_CORE17", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when temperature is the upper limit on frequency", + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_P_DEMOTIONS_CORE2", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_P_DEMOTIONS_CORE3", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_P_DEMOTIONS_CORE4", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_P_DEMOTIONS_CORE5", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x36", + "EventName": "UNC_P_DEMOTIONS_CORE6", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_P_DEMOTIONS_CORE7", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x38", + "EventName": "UNC_P_DEMOTIONS_CORE8", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_P_DEMOTIONS_CORE9", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Thermal Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "freq_max_limit_thermal_cycles %", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when the OS is the upper limit on frequency", + "BriefDescription": "OS Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_FREQ_MAX_OS_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_OS_CYCLES / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "freq_max_os_cycles %", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when power is the upper limit on frequency", + "BriefDescription": "Power Strongest Upper Limit Cycles", "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", - "MetricExpr": "(UNC_P_FREQ_MAX_POWER_CYCLES / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "freq_max_power_cycles %", "PerPkg": "1", "Unit": "PCU" }, { - "BriefDescription": "Counts the number of cycles when current is the upper limit on frequency", + "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Cycles spent changing Frequency", "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", - "MetricExpr": "(UNC_P_FREQ_TRANS_CYCLES / UNC_P_CLOCKTICKS) * 100.", - "MetricName": "freq_trans_cycles %", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x2F", + "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", + "EventCode": "0xA", + "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", + "EventCode": "0x9", + "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", + "EventCode": "0x72", + "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_P_VR_HOT_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", + "EventCode": "0x2A", + "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", + "EventCode": "0x2B", + "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", + "EventCode": "0x2C", + "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", + "EventCode": "0x2D", + "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C7 State Residency", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C1E", + "Counter": "0,1,2,3", + "EventCode": "0x4E", + "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES", "PerPkg": "1", "Unit": "PCU" } |