diff options
Diffstat (limited to 'tools/testing/selftests/kvm/riscv/get-reg-list.c')
| -rw-r--r-- | tools/testing/selftests/kvm/riscv/get-reg-list.c | 86 |
1 files changed, 47 insertions, 39 deletions
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 9f99ea42f45f..a61b706a8778 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -25,6 +25,8 @@ bool filter_reg(__u64 reg) * the visibility of the ISA_EXT register itself. * * Based on above, we should filter-out all ISA_EXT registers. + * + * Note: The below list is alphabetically sorted. */ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C: @@ -33,21 +35,21 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVNAPOT: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM: return true; /* AIA registers are always available when Ssaia can't be disabled */ @@ -311,35 +313,38 @@ static const char *fp_d_id_to_str(const char *prefix, __u64 id) return NULL; } +#define KVM_ISA_EXT_ARR(ext) \ +[KVM_RISCV_ISA_EXT_##ext] = "KVM_RISCV_ISA_EXT_" #ext + static const char *isa_ext_id_to_str(__u64 id) { /* reg_off is the offset into unsigned long kvm_isa_ext_arr[] */ __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT); static const char * const kvm_isa_ext_reg_name[] = { - "KVM_RISCV_ISA_EXT_A", - "KVM_RISCV_ISA_EXT_C", - "KVM_RISCV_ISA_EXT_D", - "KVM_RISCV_ISA_EXT_F", - "KVM_RISCV_ISA_EXT_H", - "KVM_RISCV_ISA_EXT_I", - "KVM_RISCV_ISA_EXT_M", - "KVM_RISCV_ISA_EXT_SVPBMT", - "KVM_RISCV_ISA_EXT_SSTC", - "KVM_RISCV_ISA_EXT_SVINVAL", - "KVM_RISCV_ISA_EXT_ZIHINTPAUSE", - "KVM_RISCV_ISA_EXT_ZICBOM", - "KVM_RISCV_ISA_EXT_ZICBOZ", - "KVM_RISCV_ISA_EXT_ZBB", - "KVM_RISCV_ISA_EXT_SSAIA", - "KVM_RISCV_ISA_EXT_V", - "KVM_RISCV_ISA_EXT_SVNAPOT", - "KVM_RISCV_ISA_EXT_ZBA", - "KVM_RISCV_ISA_EXT_ZBS", - "KVM_RISCV_ISA_EXT_ZICNTR", - "KVM_RISCV_ISA_EXT_ZICSR", - "KVM_RISCV_ISA_EXT_ZIFENCEI", - "KVM_RISCV_ISA_EXT_ZIHPM", + KVM_ISA_EXT_ARR(A), + KVM_ISA_EXT_ARR(C), + KVM_ISA_EXT_ARR(D), + KVM_ISA_EXT_ARR(F), + KVM_ISA_EXT_ARR(H), + KVM_ISA_EXT_ARR(I), + KVM_ISA_EXT_ARR(M), + KVM_ISA_EXT_ARR(V), + KVM_ISA_EXT_ARR(SSAIA), + KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVINVAL), + KVM_ISA_EXT_ARR(SVNAPOT), + KVM_ISA_EXT_ARR(SVPBMT), + KVM_ISA_EXT_ARR(ZBA), + KVM_ISA_EXT_ARR(ZBB), + KVM_ISA_EXT_ARR(ZBS), + KVM_ISA_EXT_ARR(ZICBOM), + KVM_ISA_EXT_ARR(ZICBOZ), + KVM_ISA_EXT_ARR(ZICNTR), + KVM_ISA_EXT_ARR(ZICSR), + KVM_ISA_EXT_ARR(ZIFENCEI), + KVM_ISA_EXT_ARR(ZIHINTPAUSE), + KVM_ISA_EXT_ARR(ZIHPM), }; if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) { @@ -353,19 +358,22 @@ static const char *isa_ext_id_to_str(__u64 id) return kvm_isa_ext_reg_name[reg_off]; } +#define KVM_SBI_EXT_ARR(ext) \ +[ext] = "KVM_REG_RISCV_SBI_SINGLE | " #ext + static const char *sbi_ext_single_id_to_str(__u64 reg_off) { /* reg_off is KVM_RISCV_SBI_EXT_ID */ static const char * const kvm_sbi_ext_reg_name[] = { - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR", + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_V01), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_TIME), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_IPI), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_RFENCE), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SRST), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_HSM), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR), }; if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) { |