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* Merge branch 'lorenzo/pci/dwc-msi'Bjorn Helgaas2018-04-0412-370/+256
|\ | | | | | | | | | | | | * lorenzo/pci/dwc-msi: PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256 PCI: dwc: Remove old MSI IRQs API PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API
| * PCI: dwc: Expand maximum number of MSI IRQs from 32 to 256Gustavo Pimentel2018-03-062-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Synopsys PCIe Root Complex supports up to MSI 256 IRQs distributed over 8 controller registers, therefore the maximum number of MSI IRQs can be changed to 256. The number of controllers can be calculated based on the number of vectors used by the specific SoC driver. Update the dwc host bridge driver maximum number of supported MSI IRQs. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Niklas Cassel <niklas.cassel@axis.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
| * PCI: dwc: Remove old MSI IRQs APIGustavo Pimentel2018-03-065-195/+5
| | | | | | | | | | | | | | | | | | | | | | Remove the unused old MSI IRQs API from pcie-designware based on struct msi_controller that should now be considered obsolete. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Niklas Cassel <niklas.cassel@axis.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
| * PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical APIGustavo Pimentel2018-03-0611-214/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a multiplexed IRQ domain hierarchy API in the pcie-designware host bridge driver that funnels all MSI IRQs into a single parent interrupt, moving away from the obsolete struct msi_controller based API. Although the old implementation API is still available, pcie-designware will now use the multiplexed IRQ domains hierarchical API. Remove all existing dwc based host bridges MSI IRQs handlers, in that the hierarchical API now handles MSI IRQs through the hierarchical/chained MSI domain implementation. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Niklas Cassel <niklas.cassel@axis.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
* | Merge branch 'lorenzo/pci/dwc'Bjorn Helgaas2018-04-045-43/+67
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * lorenzo/pci/dwc: PCI: histb: Add an optional regulator for PCIe port power control PCI: histb: Fix error path of histb_pcie_host_enable() PCI: qcom: Use regulator bulk api for apq8064 supplies PCI: qcom: Add missing supplies required for msm8996 PCI: designware-ep: Fix typo in error message
| * | PCI: histb: Add an optional regulator for PCIe port power controlShawn Guo2018-03-072-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The power supplies to PCIe port are often controlled by GPIO on some board designs. Let's add an optional regulator which can be backed by GPIO to control the power. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Rob Herring <robh@kernel.org>
| * | PCI: histb: Fix error path of histb_pcie_host_enable()Shawn Guo2018-03-071-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | If clk_prepare_enable() call fails on a particular clock, we should not call clk_disable_unprepare() on this clock, but on the clocks that succeed from clk_prepare_enable() previously. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: qcom: Use regulator bulk api for apq8064 suppliesSrinivas Kandagatla2018-03-071-37/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch converts existing regulators to use regulator bulk apis, to make it consistent with msm8996 changes also cut down some redundant code. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | PCI: qcom: Add missing supplies required for msm8996Srinivas Kandagatla2018-03-072-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds supplies that are required for msm8996. vdda is analog supply that go in to controller, and vddpe_3v3 is supply to PCIe endpoint. Without these supplies PCIe endpoints which require power supplies are not enumerated at all, as there is no one to power it up. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> Reviewed-by: Rob Herring <robh@kernel.org>
| * | PCI: designware-ep: Fix typo in error messageNiklas Cassel2018-03-071-1/+1
| |/ | | | | | | | | | | | | Fix typo in error message. s/deb_base2/dbi_base2/ Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* | Merge branch 'lorenzo/pci/altera'Bjorn Helgaas2018-04-041-1/+1
|\ \ | | | | | | | | | | | | * lorenzo/pci/altera: PCI: altera: Fix bool initialization in tlp_read_packet()
| * | PCI: altera: Fix bool initialization in tlp_read_packet()Gustavo A. R. Silva2018-02-281-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Bool variables should be initialized only through true and false values; update tlp_read_packet() code to comply. Detected using the Coccinelle tool. Fixes: eaa6111b70a7 ("PCI: altera: Add Altera PCIe host controller driver") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | Merge branch 'pci/vpd'Bjorn Helgaas2018-04-045-570/+578
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | - consolidate VPD code in vpd.c (Bjorn Helgaas) * pci/vpd: PCI/VPD: Move VPD structures to vpd.c PCI/VPD: Move VPD quirks to vpd.c PCI/VPD: Move VPD sysfs code to vpd.c PCI/VPD: Move VPD access code to vpd.c
| * | PCI/VPD: Move VPD structures to vpd.cBjorn Helgaas2018-03-192-17/+17
| | | | | | | | | | | | | | | | | | | | | The VPD-related structures are only used in vpd.c, so move them from drivers/pci/pci.h to vpd.c. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/VPD: Move VPD quirks to vpd.cBjorn Helgaas2018-03-192-121/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the VPD-related quirks from quirks.c to vpd.c, which removes the need for struct pci_vpd outside vpd.c. The goal is to encapsulate all the VPD code and structures in vpd.c. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/VPD: Move VPD sysfs code to vpd.cBjorn Helgaas2018-03-193-64/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the VPD-related sysfs code from pci-sysfs.c to vpd.c. This follows the pattern of pcie_aspm_create_sysfs_dev_files(). The goal is to encapsulate all the VPD code and structures in vpd.c. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/VPD: Move VPD access code to vpd.cBjorn Helgaas2018-03-192-368/+369
| |/ | | | | | | | | | | | | | | | | Move the VPD-related code from access.c to vpd.c. The goal is to encapsulate all the VPD code and structures in vpd.c. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/virtualization'Bjorn Helgaas2018-04-048-51/+168
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - probe for device reset support during enumeration instead of runtime (Bjorn Helgaas) - add ACS quirk for Ampere (née APM) root ports (Feng Kan) - add function 1 DMA alias quirk for Marvell 88SE9220 (Thomas Vincent-Cross) - protect device restore with device lock (Sinan Kaya) - handle failure of FLR gracefully (Sinan Kaya) - handle CRS (config retry status) after device resets (Sinan Kaya) - skip various config reads for SR-IOV VFs as an optimization (KarimAllah Ahmed) * pci/virtualization: PCI/IOV: Add missing prototypes for powerpc pcibios interfaces PCI/IOV: Use VF0 cached config registers for other VFs PCI/IOV: Skip BAR sizing for VFs PCI/IOV: Skip INTx config reads for VFs PCI: Wait for device to become ready after secondary bus reset PCI: Add a return type for pci_reset_bridge_secondary_bus() PCI: Wait for device to become ready after a power management reset PCI: Rename pci_flr_wait() to pci_dev_wait() and make it generic PCI: Handle FLR failure and allow other reset types PCI: Protect restore with device lock to be consistent PCI: Add function 1 DMA alias quirk for Marvell 88SE9220 PCI: Add ACS quirk for Ampere root ports PCI: Remove redundant probes for device reset support PCI: Probe for device reset support during enumeration Conflicts: include/linux/pci.h
| * | PCI/IOV: Add missing prototypes for powerpc pcibios interfacesMathieu Malaterre2018-03-311-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing prototypes for: resource_size_t pcibios_default_alignment(void); int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); int pcibios_sriov_disable(struct pci_dev *pdev); This fixes the following warnings treated as errors when using W=1: arch/powerpc/kernel/pci-common.c:236:17: error: no previous prototype for ‘pcibios_default_alignment’ [-Werror=missing-prototypes] arch/powerpc/kernel/pci-common.c:253:5: error: no previous prototype for ‘pcibios_sriov_enable’ [-Werror=missing-prototypes] arch/powerpc/kernel/pci-common.c:261:5: error: no previous prototype for ‘pcibios_sriov_disable’ [-Werror=missing-prototypes] Also, commit 978d2d683123 ("PCI: Add pcibios_iov_resource_alignment() interface") added a new function but the prototype was located in the main header instead of the CONFIG_PCI_IOV specific section. Move this function next to the newly added ones. Signed-off-by: Mathieu Malaterre <malat@debian.org> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
| * | PCI/IOV: Use VF0 cached config registers for other VFsKarimAllah Ahmed2018-03-313-12/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cache some config data from VF0 and use it for all other VFs instead of reading it from the config space of each VF. We assume these items are the same across all associated VFs: Revision ID Class Code Subsystem Vendor ID Subsystem ID This is an optimization when enabling SR-IOV on a device with many VFs. Signed-off-by: KarimAllah Ahmed <karahmed@amazon.de> [bhelgaas: changelog, simplify comments, remove unused "device", test CONFIG_PCI_IOV instead of CONFIG_PCI_ATS, rename functions] Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
| * | PCI/IOV: Skip BAR sizing for VFsKarimAllah Ahmed2018-03-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per PCIe r4.0, sec 9.3.4.1.11, the BAR registers in VF config space are all RO Zero, so skip sizing them. This is an optimization when enabling SR-IOV on a device with many VFs. Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: KarimAllah Ahmed <karahmed@amazon.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/IOV: Skip INTx config reads for VFsKarimAllah Ahmed2018-03-051-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per PCIe r4.0, sec 9.2.1.4, VFs can not implement INTX, and their Interrupt Line and Interrupt Pin registers must be RO Zero. Some devices have thousands of VFs, so skip reading the registers as an optimization. Signed-off-by: KarimAllah Ahmed <karahmed@amazon.de> Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de> [bhelgaas: changelog, comment] Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
| * | PCI: Wait for device to become ready after secondary bus resetSinan Kaya2018-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting Secondary Bus Reset of a downstream port sends a hot reset. PCIe r4.0, sec 2.3.1, Request Handling Rules, indicates that a device can return CRS Completion Status following such a reset. Wait until the device becomes ready in that situation. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI: Add a return type for pci_reset_bridge_secondary_bus()Sinan Kaya2018-03-052-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a return value to pci_reset_bridge_secondary_bus() so we can return an error if the device doesn't become ready after the reset. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI: Wait for device to become ready after a power management resetSinan Kaya2018-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe r4.0, sec 2.3.1, Request Handling Rules, indicates that a device can return CRS Completion Status following a D3hot to D0 transition. Wait until the device becomes ready in that situation. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI: Rename pci_flr_wait() to pci_dev_wait() and make it genericSinan Kaya2018-02-271-17/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe r4.0, sec 2.3.1, Request Handling Rules, says: Valid reset conditions after which a device is permitted to return CRS are: * Cold, Warm, and Hot Resets, * FLR * A reset initiated in response to a D3hot to D0 uninitialized Try to reuse FLR implementation towards other reset types. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Handle FLR failure and allow other reset typesSinan Kaya2018-02-272-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci_flr_wait() and pci_af_flr() functions assume graceful return even though the device is inaccessible under error conditions. Return -ENOTTY in error cases so that __pci_reset_function_locked() can try other reset types if AF_FLR/FLR reset fails. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI: Protect restore with device lock to be consistentSinan Kaya2018-02-271-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b014e96d1abb ("PCI: Protect pci_error_handlers->reset_notify() usage with device_lock()") added protection around pci_dev_restore() function so a device-specific remove callback does not cause a race condition with hotplug. pci_dev_lock() usage has been forgotten in two places. Add locks for pci_slot_restore() and moving pci_dev_restore() inside the locks for pci_try_reset_function(). Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI: Add function 1 DMA alias quirk for Marvell 88SE9220Thomas Vincent-Cross2018-02-271-0/+3
| | | | | | | | | | | | | | | | | | | | | Add Marvell 88SE9220 DMA quirk as found and tested on bug 42679. Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679 Signed-off-by: Thomas Vincent-Cross <me@tvc.id.au> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
| * | PCI: Add ACS quirk for Ampere root portsFeng Kan2018-02-222-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Ampere Computing PCIe root port does not support ACS at this point. However, the hardware provides isolation and source validation through the SMMU. The stream ID generated by the PCIe ports contain both the bus/device/function number as well as the port ID in its 3 most significant bits. Turn on ACS but disable all the peer-to-peer features. APM is being rebranded to Ampere. The Vendor and Device IDs change, but the functionality stays the same. Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
| * | PCI: Remove redundant probes for device reset supportBjorn Helgaas2018-02-211-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We probe every device for whether it supports reset so we can tell whether to create a sysfs "reset" file for it. We do that probe in pci_init_capabilities() during enumeration and save the result in dev->reset_fn. The result doesn't depend on any other devices on the bus and shouldn't change after boot, so we don't need to do the probe again. Remove the pci_probe_reset_function() calls and rely on the dev->reset_fn we found during enumeration. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | PCI: Probe for device reset support during enumerationBjorn Helgaas2018-02-162-2/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we called pci_probe_reset_function() in this path: pci_sysfs_init # late_initcall for_each_pci_dev(dev) pci_create_sysfs_dev_files(dev) pci_create_capabilities_sysfs(dev) pci_probe_reset_function pci_dev_specific_reset pcie_has_flr pcie_capability_read_dword pci_sysfs_init() is a late_initcall, and a driver may have already claimed one of these devices and enabled runtime power management for it, so the device could already be in D3 by the time we get to pci_sysfs_init(). The device itself should respond to the config read even while it's in D3hot, but if an upstream bridge is also in D3hot, the read won't even reach the device because the bridge won't forward it downstream to the device. If the bridge is a PCIe port, it should complete the read as an Unsupported Request, which may be reported to the CPU as an exception or as invalid data. Avoid this case by probing for reset support from pci_init_capabilities(), before a driver can claim the device. The device may be in D3hot, but any bridges leading to it should be in D0, so the device's config space should be fully accessible at that point. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | Merge branch 'pci/sparc'Bjorn Helgaas2018-04-043-31/+33
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | - support arbitrary PCI host bridge offsets on sparc (Yinghai Lu) - remove System and Video ROM reservations on sparc (Bjorn Helgaas) * pci/sparc: sparc/PCI: Stop reserving System ROM and Video ROM in PCI space sparc/PCI: Support arbitrary host bridge address offset
| * | sparc/PCI: Stop reserving System ROM and Video ROM in PCI spaceBjorn Helgaas2018-03-201-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, pci_register_legacy_regions() reserved PCI address space under every PCI host bridge for the System ROM and the Video ROM, but these regions are not part of PCI address space. Previously, pci_register_legacy_regions() reserved the following areas of PCI address space under every PCI host bridge: [bus 0xa0000-0xbffff] Video RAM area (VGA frame buffer) [bus 0xc0000-0xc7fff] Video ROM [bus 0xf0000-0xfffff] System ROM It does need to reserve the [bus 0xa0000-0xbffff] region (at least if there's a possibility of a VGA device below the bridge) because VGA devices can respond to that even if they don't describe it with a BAR. But the Video ROM and System ROM areas don't seem necessary because they are not areas that legacy PCI devices respond to. They appear to be copied from x86, where they describe areas of system memory that depend on BIOS conventions. On x86, BIOS copies the option ROM of the primary VGA device to RAM at 0xc0000, and the 0xf0000-0xfffff region is reserved for the motherboard BIOS. Neither of these things applies to sparc. Stop reserving the System ROM and Video ROM regions in PCI space. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: David S. Miller <davem@davemloft.net>
| * | sparc/PCI: Support arbitrary host bridge address offsetYinghai Lu2018-02-153-11/+33
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for arbitrary bus address offset. Previously we ignored the child (PCI) address in the "ranges" property and assumed it was always zero. That means every host bridge window mapped to PCI bus address zero, e.g., pci_bus 0000:00: root bus resource [mem 0x2000000000000-0x200007fffffff] (bus address [0x00000000-0x7fffffff]) But some systems have host bridge windows with non-zero child addresses, so parse the child address and compute the offset between the parent (CPU) and child (PCI) addresses. This allows windows like these: /pci@305: PCI MEM [mem 0x2000000100000-0x200007effffff] offset 2000000000000 pci_sun4v f02ae7f8: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x2000000100000-0x200007effffff] (bus address [0x00100000-0x7effffff]) [bhelgaas: changelog] Tested-by: Khalid Aziz <khalid.aziz@oracle.com> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: David S. Miller <davem@davemloft.net> Cc: sparclinux@vger.kernel.org
* | Merge branch 'pci/resource-mmap'Bjorn Helgaas2018-04-044-189/+27
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | - use generic pci_mmap_resource_range() instead of powerpc and xtensa arch-specific versions (David Woodhouse) * pci/resource-mmap: xtensa/PCI: Use generic pci_mmap_resource_range() powerpc/pci: Use generic pci_mmap_resource_range()
| * | xtensa/PCI: Use generic pci_mmap_resource_range()David Woodhouse2018-02-282-89/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f719582435 ("PCI: Add pci_mmap_resource_range() and use it for ARM64") added this generic function with the intent of using it everywhere and ultimately killing the old arch-specific implementations. Remove the xtensa-specific pci_mmap_page_range() and use the generic pci_mmap_resource_range() instead. Xtensa can mmap I/O port space, so supply the xtensa-specific pci_iobar_pfn() required to make that work. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <helgaas@kernel.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com>
| * | powerpc/pci: Use generic pci_mmap_resource_range()David Woodhouse2018-02-282-100/+15
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f719582435 ("PCI: Add pci_mmap_resource_range() and use it for ARM64") added this generic function with the intent of using it everywhere and ultimately killing the old arch-specific implementations. Remove the powerpc-specific pci_mmap_page_range() and use the generic pci_mmap_resource_range() instead. Powerpc can mmap I/O port space, so supply the powerpc-specific pci_iobar_pfn() required to make that work. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
* | Merge branch 'pci/portdrv'Bjorn Helgaas2018-04-0421-284/+215
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - move pcieport_if.h to drivers/pci/pcie/ to encapsulate it (Frederick Lawler) - merge pcieport_if.h into portdrv.h (Bjorn Helgaas) - move workaround for BIOS PME issue from portdrv to PCI core (Bjorn Helgaas) - completely disable portdrv with "pcie_ports=compat" (Bjorn Helgaas) - remove portdrv link order dependency (Bjorn Helgaas) - remove support for unused VC portdrv service (Bjorn Helgaas) - simplify portdrv feature permission checking (Bjorn Helgaas) - remove "pcie_hp=nomsi" parameter (use "pci=nomsi" instead) (Bjorn Helgaas) - remove unnecessary "pcie_ports=auto" parameter (Bjorn Helgaas) - use cached AER capability offset (Frederick Lawler) - don't enable DPC if BIOS hasn't granted AER control (Mika Westerberg) - rename pcie-dpc.c to dpc.c (Bjorn Helgaas) * pci/portdrv: PCI/DPC: Rename from pcie-dpc.c to dpc.c PCI/DPC: Do not enable DPC if AER control is not allowed by the BIOS PCI/AER: Use cached AER Capability offset PCI/portdrv: Rename and reverse sense of pcie_ports_auto PCI/portdrv: Encapsulate pcie_ports_auto inside the port driver PCI/portdrv: Remove unnecessary "pcie_ports=auto" parameter PCI/portdrv: Remove "pcie_hp=nomsi" kernel parameter PCI/portdrv: Remove unnecessary include of <linux/pci-aspm.h> PCI/portdrv: Simplify PCIe feature permission checking PCI/portdrv: Remove unused PCIE_PORT_SERVICE_VC PCI/portdrv: Remove pcie_port_bus_type link order dependency PCI/portdrv: Disable port driver in compat mode PCI/PM: Clear PCIe PME Status bit for Root Complex Event Collectors PCI/PM: Clear PCIe PME Status bit in core, not PCIe port driver PCI/PM: Move pcie_clear_root_pme_status() to core PCI/portdrv: Merge pcieport_if.h into portdrv.h PCI/portdrv: Move pcieport_if.h to drivers/pci/pcie/ Conflicts: drivers/pci/pcie/Makefile drivers/pci/pcie/portdrv.h
| * | PCI/DPC: Rename from pcie-dpc.c to dpc.cBjorn Helgaas2018-03-312-1/+1
| | | | | | | | | | | | | | | | | | Rename pcie-dpc.c to dpc.c. The path "drivers/pci/pcie/pcie-dpc.c" has more occurrences of "pci" than necessary. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/DPC: Do not enable DPC if AER control is not allowed by the BIOSMika Westerberg2018-03-302-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit eed85ff4c0da ("PCI/DPC: Enable DPC only if AER is available") made DPC control dependent whether AER is enabled in the OS. However, it does not take into account situations where BIOS has not given OS control of AER: acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] acpi PNP0A08:00: _OSC: platform does not support [AER] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME PCIeCapability] I think here it is better not to enable DPC even if the capability is available because then it would be against what "Determination of DPC Control" note in PCIe 4.0 sec 6.1.10 recommends. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
| * | PCI/AER: Use cached AER Capability offsetFrederick Lawler2018-03-303-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace pci_find_ext_capability(..., PCI_EXT_CAP_ID_ERR) calls with pci_dev->aer_cap. pci_dev->aer_cap is initialized in pci_init_capabilities(), which happens before any of these users of the AER Capability. Signed-off-by: Frederick Lawler <fred@fredlawl.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/portdrv: Rename and reverse sense of pcie_ports_autoBjorn Helgaas2018-03-303-20/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The platform may restrict the OS's use of PCIe services, e.g., via the ACPI _OSC method. The user may use "pcie_ports=native" to force the port driver to use PCIe services even if the platform asked us not to. The "pcie_ports=native" parameter determines the setting of pcie_ports_auto. Rename this to pcie_ports_native and reverse the sense to simplify the code. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/portdrv: Encapsulate pcie_ports_auto inside the port driverBjorn Helgaas2018-03-302-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | "pcie_ports_auto" is only used inside the PCIe port driver itself, so move it from include/linux/pci.h to portdrv.h so it's not visible to the whole kernel. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/portdrv: Remove unnecessary "pcie_ports=auto" parameterBjorn Helgaas2018-03-302-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "pcie_ports=auto" parameter set pcie_ports_disabled and pcie_ports_auto to their compiled-in defaults, so specifying the parameter is the same as not using it at all. Remove the "pcie_ports=auto" parameter and update the documentation. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/portdrv: Remove "pcie_hp=nomsi" kernel parameterBjorn Helgaas2018-03-303-33/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 7570a333d8b0 ("PCI: Add pcie_hp=nomsi to disable MSI/MSI-X for pciehp driver") added the "pcie_hp=nomsi" kernel parameter to work around this error on shutdown: irq 16: nobody cared (try booting with the "irqpoll" option) Pid: 1081, comm: reboot Not tainted 3.2.0 #1 ... Disabling IRQ #16 This happened on an unspecified system (possibly involving the Integrated Device Technology, Inc. Device 807f bridge) where "an un-wanted interrupt is generated when PCI driver switches from MSI/MSI-X to INTx while shutting down the device." The implication was that the device was buggy, but it is normal for a device to use INTx after MSI/MSI-X have been disabled. The only problem was that the driver was still attached and it wasn't prepared for INTx interrupts. Prarit Bhargava fixed this issue with fda78d7a0ead ("PCI/MSI: Stop disabling MSI/MSI-X in pci_device_shutdown()"). There is no automated way to set this parameter, so it's not very useful for distributions or end users. It's really only useful for debugging, and we have "pci=nomsi" for that purpose. Revert 7570a333d8b0 to remove the "pcie_hp=nomsi" parameter. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> CC: MUNEDA Takahiro <muneda.takahiro@jp.fujitsu.com> CC: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> CC: Prarit Bhargava <prarit@redhat.com>
| * | PCI/portdrv: Remove unnecessary include of <linux/pci-aspm.h>Bjorn Helgaas2018-03-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | portdrv_pci.c doesn't use anything from <linux/pci-aspm.h>. Remove the include of it. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | PCI/portdrv: Simplify PCIe feature permission checkingBjorn Helgaas2018-03-306-30/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some PCIe features (AER, DPC, hotplug, PME) can be managed by either the platform firmware or the OS, so the host bridge driver may have to request permission from the platform before using them. On ACPI systems, this is done by negotiate_os_control() in acpi_pci_root_add(). The PCIe port driver later uses pcie_port_platform_notify() and pcie_port_acpi_setup() to figure out whether it can use these features. But all we need is a single bit for each service, so these interfaces are needlessly complicated. Simplify this by adding bits in the struct pci_host_bridge to show when the OS has permission to use each feature: + unsigned int native_aer:1; /* OS may use PCIe AER */ + unsigned int native_hotplug:1; /* OS may use PCIe hotplug */ + unsigned int native_pme:1; /* OS may use PCIe PME */ These are set when we create a host bridge, and the host bridge driver can clear the bits corresponding to any feature the platform doesn't want us to use. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | PCI/portdrv: Remove unused PCIE_PORT_SERVICE_VCBjorn Helgaas2018-03-303-15/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No driver registers for PCIE_PORT_SERVICE_VC, so remove it. This removes the VC "service" files from /sys/bus/pci_express/devices, e.g., 0000:07:00.0:pcie108, 0000:08:04.0:pcie208 (all the files that contained "8" as the last digit of the "pcieXXX" part). The port driver created these files for PCIe port devices that have a VC Capability. Since this reduces PCIE_PORT_DEVICE_MAXSERVICES and moves DPC down into the spot where VC used to be, the DPC sysfs files will now be named "pcieXX8". I don't think there's anything useful userspace can do with those files, so I hope nobody cares about these filenames. There is no VC driver that calls pcie_port_service_register(), so there never was a /sys/bus/pci_express/drivers/vc directory. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/portdrv: Remove pcie_port_bus_type link order dependencyBjorn Helgaas2018-03-304-69/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pcie_port_bus_type must be registered before drivers that depend on it can be registered. Those drivers include: pcied_init() # PCIe native hotplug driver aer_service_init() # AER driver dpc_service_init() # DPC driver pcie_pme_service_init() # PME driver Previously we registered pcie_port_bus_type from pcie_portdrv_init(), a device_initcall. The callers of pcie_port_service_register() (above) are also device_initcalls. This is fragile because the device_initcall ordering depends on link order, which is not explicit. Register pcie_port_bus_type from pci_driver_init() along with pci_bus_type. This removes the link order dependency between portdrv and the pciehp, AER, DPC, and PCIe PME drivers. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 12:40:25 +0000