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* Merge tag 'amlogic-dt64' of ↵Arnd Bergmann2017-12-2112-11/+192
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Pull "Amlogic 64-bit DT updates for v4.16" from Kevin Hilman - meson-gx: add VPU power domain support - odroid-c2: add HDMI and CEC nodes - misc cleanups * tag 'amlogic-dt64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxm: fix q200 interrupt number ARM64: dts: meson-gxm: add the PHY interrupt line on Khadas VIM2 ARM64: dts: meson: add comments with the GPIO for the PHY interrupts ARM64: dts: amlogic: use generic bus node names ARM64: dts: meson: drop "sana" clock from SAR ADC ARM64: dts: odroid-c2: Add HDMI and CEC Nodes ARM64: dts: meson-gx: grow reset controller memory zone ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards ARM64: dts: meson-gx: add VPU power domain
| * ARM64: dts: meson-gxm: fix q200 interrupt numberJerome Brunet2017-12-081-2/+2
| | | | | | | | | | | | | | | | | | Correct the interrupt number assigned to the Realtek PHY in the q200 Fixes: b94d22d94ad2 ("ARM64: dts: meson-gx: add external PHY interrupt on some platforms") Reported-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * ARM64: dts: meson-gxm: add the PHY interrupt line on Khadas VIM2Martin Blumenstingl2017-12-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | The INTB/PMEB pin of the RTL8211F PHY on the Khadas VIM2 is routed to GPIOZ_15. Add the corresponding interrupt using the GPIO interrupt controller so the PHY framework doesn't have to poll the PHY for it's status. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * ARM64: dts: meson: add comments with the GPIO for the PHY interruptsMartin Blumenstingl2017-12-084-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently one has to look/calculate the GPIO for the PHY interrupts manually. Add a comment for the existing PHY interrupt lines to make it easier to find out which GPIO is used. This is done using the following calculation: - number of GPIO AO pins (14 on GXBB: GPIOAO_0..13) - add the offset of the pin which is used for the interrupt (for example GPIOZ_15 = 15 on Odroid-C2) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-By: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * ARM64: dts: amlogic: use generic bus node namesKevin Hilman2017-12-082-5/+5
| | | | | | | | | | | | | | | | | | | | The DT spec recommends that node-names have generic names like "bus". Fix that in the Amlogic DTs, while leaving the label names to have more SoC-specific names that match with the HW documentation. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * ARM64: dts: meson: drop "sana" clock from SAR ADCXingyu Chen2017-12-062-4/+2
| | | | | | | | | | | | | | | | | | The SAR ADC modules doesn't require The "sana" clock. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Singed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * ARM64: dts: odroid-c2: Add HDMI and CEC NodesNeil Armstrong2017-12-061-0/+30
| | | | | | | | | | | | | | | | Now the VPU Power Domain has been fixed while boothing from Mainline U-Boot, VPU and HDMI nodes can finally be added to the Odroid-C2 DTS. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * ARM64: dts: meson-gx: grow reset controller memory zoneNeil Armstrong2017-12-061-1/+1
| | | | | | | | | | | | | | | | Now the Amlogic Meson GX SoCs datasheet documents all the Reset registers, grow the memory in the node to allow usage of the level registers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boardsNeil Armstrong2017-12-064-0/+48
| | | | | | | | | | | | | | | | | | On reference boards and derivatives, the HDMI Logic is powered by an external 5V regulator. This regulator was set by the Vendor U-Boot, add the regulator and set it always-on for now. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * ARM64: dts: meson-gx: add VPU power domainNeil Armstrong2017-12-063-0/+97
| | | | | | | | | | | | | | | | This patch adds support for the VPU Power Domain nodes, and attaches the VPU power domain to the VPU node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | Merge tag 'amlogic-dt' of ↵Arnd Bergmann2017-12-213-14/+40
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Pull "Amlogic 32-bit DT changes for v4.16" from Kevin Hilman: - meson8: GPIO IRQ support - switch to stable UART bindings w/correct clock - add more L2 cache settings - drop unused ADC clock * tag 'amlogic-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: meson: enable MESON_IRQ_GPIO also for MACH_MESON8 ARM: dts: meson8: enable the GPIO interrupt controller ARM: dts: meson8b: use stable UART bindings with correct gate clock ARM: dts: meson8: use stable UART bindings with correct gate clock ARM: dts: meson: drop "sana" clock from SAR ADC ARM: dts: meson8: add more L2 cache settings ARM: dts: meson8b: add more L2 cache settings
| * | ARM: meson: enable MESON_IRQ_GPIO also for MACH_MESON8Martin Blumenstingl2017-12-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Now that the GPIO interrupt controller also supports the Meson8 SoCs we can enable it via Kconfig. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * | ARM: dts: meson8: enable the GPIO interrupt controllerMartin Blumenstingl2017-12-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the GPIO interrupt controller for the Meson8 SoCs. Interrupt support on the GPIOs can be used by the MMC framework to detect when an SD card is inserted/removed or by the input framework to detect button presses. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * | ARM: dts: meson8b: use stable UART bindings with correct gate clockMartin Blumenstingl2017-12-061-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to the stable UART bindings and add the correct gate clocks to the non-AO UART nodes. This fixes the non-AO UARTs if the bootloader didn't un-gate the clocks. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * | ARM: dts: meson8: use stable UART bindings with correct gate clockMartin Blumenstingl2017-12-061-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to the stable UART bindings and add the correct gate clocks to the non-AO UART nodes. This fixes the non-AO UARTs if the bootloader didn't un-gate the clocks. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * | ARM: dts: meson: drop "sana" clock from SAR ADCXingyu Chen2017-12-062-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SAR ADC modules doesn't require The "sana" clock. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * | ARM: dts: meson8: add more L2 cache settingsMartin Blumenstingl2017-12-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Amlogic's vendor kernel prints these PL310 L2 cache controller settings during boot: 8 ways, 4096 sets, CACHE_ID 0x4100a0c9, Cache size: 1048576 B AUX_CTRL 0x7ec80001, PERFETCH_CTRL 0x71000007, POWER_CTRL 0x00000000 TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222 Add the "prefetch-data", "prefetch-instr" and "arm,shared-override" properties to get the same L2 cache controller configuration as the vendor kernel. Two differences still remain: - L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0 driver - bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * | ARM: dts: meson8b: add more L2 cache settingsMartin Blumenstingl2017-12-061-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Amlogic's vendor kernel prints these PL310 L2 cache controller settings during boot: 8 ways, 2048 sets, CACHE_ID 0x4100a0c9, Cache size: 524288 B AUX_CTRL 0x7ec60001, PERFETCH_CTRL 0x75000007, POWER_CTRL 0x00000000 TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222 Add the "prefetch-data", "prefetch-instr" and "arm,shared-override" properties to get the same L2 cache controller configuration as the vendor kernel. Four differences still remain: - L310_AUX_CTRL_EARLY_BRESP is enabled by the vendor kernel, however this is only supported on Cortex-A9 cores (Meson8b has Cortex-A5 cores though) - L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0 driver - bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h - L310_AUX_CTRL_FULL_LINE_ZERO is enabled by the vendor kernel which is also only supported on Cortex-A9 cores Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | Merge tag 'renesas-arm64-dt-for-v4.16' of ↵Arnd Bergmann2017-12-2115-49/+947
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Pull "Renesas ARM64 Based SoC DT Updates for v4.16" from Simon Horman: * Use r8a77970 (V3M) CPG core clock and SYSC power domain macros These may be used in place of numeric constants now that they are present in Linus's tree. * Add r8a77970 (V3M) Starter Kit board support This includes basic support to bring up the board with a serial console and EtherAVB support * Add IPMMU nodes and connections to on-chip devices on r8a7795 (H3), r8a7796 (M3-W), r8a77970 (V3M) and r8a77995 (D3) SoCs Simon Horman says "With these patches applied a white list enabled IPMMU driver may be used to check silicon revision and then enable IPMMU in the known working cases." * Enable DMA for SCIF2 on r8a77995 (D2) SoC * Increase the number of GPIO bank 1 ports to 29 on r8a7795 (H3) SoC This adds support for the GP-1-28 port pin of the r8a7795 (H3) ES2.0 SoC * Add support for CAN to r8a77995 (D3) SoC Ulrich Hecht says "This is a by-the-datasheet implementation, with the datasheet missing some bits, namely the pin map. I filled in the gaps... by deducing the information from pin numbers already in the PFC driver, so careful scrutiny is advised." * Add support for SDHI to r8a77995 (D3) SoC * Add SoC name to file header of r8a7795 (H3) and r8a7796 (M3-W) Salvator-X and Salvator-XS board files Geert Uytterhoeven says "With the proliferation of Salvator-X and Salvator-XS boards carrying different R-Car Gen3 SoCs variants, several DTS files ended up having the same file headers. Add the SoC names to the file headers to avoid confusion." * Add device note for ROHM BD9571MWV PMIC to r8a7795 (H3) and r8a7796 (M3-W) Salvator-X and Salvator-XS boards. Geert Uytterhoeven says "This was based on the example in the DT binding documentation, but using IRQ0 instead of a GPIO interrupt, as that matches the schematics, and because INTC-EX is a simpler block." * Enable USB2.0 channel 0 on r8a77970 (V3M) ULCB Kingfisher board Vladimir Barinov says "The dedicated USB0_PWEN pin is used to control CN13 VBUS source from U43 power supply. MAX3355 can also provide VBUS, hence it should be disabled via OTG_OFFVBUSn node coming from gpio expander TCA9539. Set MAX3355 enabled using OTG_EXTLPn node to be able to read OTG ID of CN13." * Add support for r8a7795 (M3-W) Salvator-XS board Geert Uytterhoeven says "This patch series adds support for the version of the Salvator-XS development board equipped with an R-Car M3-W SiP. The DT was based on work for the Salvator-X and -XS boards with M3-W resp. H3 SiPs." * Add watchdog timer support to r8a77970 (V3M) eagle board Geert Uytterhoven says "This allows to use the watchdog timer to reset the board, until PSCI is enhanced to include such functionality." * Use Use R-Car SDHI Gen3 fallback on r8a7795 (H3) and r8a7796 (M3-W) SoCs * Set driver type for MMC on r8a7795 (H3) and r8a7796 (M3-W) Salvator-X and Salvator-XS boards. Wolfram Sang says "These boards are known to have eMMC issues with the default driver type. Specify a working one." * tag 'renesas-arm64-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (54 commits) arm64: dts: renesas: r8a77970: use SYSC power domain macros arm64: dts: renesas: r8a77970: use CPG core clock macros arm64: dts: renesas: v3msk: add EtherAVB support arm64: dts: renesas: initial V3MSK board device tree arm64: dts: renesas: r8a77995: Connect Ethernet-AVB to IPMMU-RT arm64: dts: renesas: r8a77995: Add IPMMU device nodes arm64: dts: renesas: r8a77970: Enable IPMMU-DS1, RT and MM arm64: dts: renesas: r8a77970: Connect Ethernet-AVB to IPMMU-RT arm64: dts: renesas: r8a77970: Tie SYS-DMAC to IPMMU-DS1 arm64: dts: renesas: r8a77970: Add IPMMU device nodes arm64: dts: renesas: r8a77995: add DMA for SCIF2 arm64: dts: renesas: r8a77970: sort includes arm64: dts: renesas: r8a7795: Increase the number of GPIO bank 1 ports to 29 arm64: dts: renesas: r8a77995: Add CAN FD support arm64: dts: renesas: r8a77995: Add CAN support arm64: dts: renesas: r8a77995: Add CAN external clock support arm64: dts: renesas: r8a7795-salvator-xs: Add SoC name to file header arm64: dts: renesas: r8a7796-salvator-x: Add SoC name to file header arm64: dts: renesas: r8a7795-salvator-x: Add SoC name to file header arm64: dts: renesas: r8a7795-es1-salvator-x: Add SoC name to file header ...
| * | arm64: dts: renesas: r8a77970: use SYSC power domain macrosSergei Shtylyov2017-12-051-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the commit 833bdb47c826 ("dt-bindings: power: add R8A77970 SYSC power domain definitions") has hit Linus' tree, we can replace the bare numbers (we had to use to avoid a cross tree dependency) with these macro definitions... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a77970: use CPG core clock macrosSergei Shtylyov2017-12-051-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the commit ecadea00f588 ("dt-bindings: clock: Add R8A77970 CPG core clock definitions") has hit Linus' tree, we can replace the bare numbers (we had to use to avoid a cross tree dependency) with these macro definitions... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: v3msk: add EtherAVB supportSergei Shtylyov2017-12-041-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the V3M Starter Kit board dependent part of the EtherAVB device node. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: initial V3MSK board device treeSergei Shtylyov2017-12-042-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the initial device tree for the V3M Starter Kit board. The board has 1 debug serial port (SCIF0); include support for it, so that the serial console can work. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a77995: Connect Ethernet-AVB to IPMMU-RTSimon Horman2017-11-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add IPMMU-RT to the Ethernet-AVB device node. Based on work by Magnus Damm for the r8a7795. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a77995: Add IPMMU device nodesSimon Horman2017-11-281-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add r8a77995 IPMMU nodes and keep all disabled by default. Based on work for the r8a7795 and r8a7796 by Magnus Damm Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a77970: Enable IPMMU-DS1, RT and MMSimon Horman2017-11-281-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the r8a77970 device nodes for IPMMU-DS1, IPMMU-RT and the shared IPMMU-MM device. Based on work for the r8a7796 by Magnus Damm. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a77970: Connect Ethernet-AVB to IPMMU-RTSimon Horman2017-11-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add IPMMU-RT to the Ethernet-AVB device node. Based on work by Magnus Damm for the r8a7795. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a77970: Tie SYS-DMAC to IPMMU-DS1Simon Horman2017-11-281-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hook up r8a77970 DMAC nodes to the IPMMU. In particular SYS-DMAC1 and SYS-DMAC2 get tied to IPMMU-DS1. Based on work for the r8a7796 by Magnus Damm. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a77970: Add IPMMU device nodesSimon Horman2017-11-281-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add r8a77970 IPMMU nodes and keep all disabled by default. Based on work for the r8a7796 by Magnus Damm Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a77995: add DMA for SCIF2Ulrich Hecht2017-11-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Tested on Draak. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a77970: sort includesSimon Horman2017-11-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Sort includes used in r8a77970 DTS to improve maintainability and for consistency with other R-Car DTS files. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a7795: Increase the number of GPIO bank 1 ports to 29Takeshi Kihara2017-11-282-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the number of GPIO bank 1 ports to 29 because GP-1-28 port pin of R8A7795 ES2.0 SoC support was added. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Fixes: 291e0c4994d0813f ("arm64: dts: r8a7795: Add support for R-Car H3 ES2.0") [geert: Keep 28 GPIOs on H3 ES1.x after r8a7795.dtsi sharing] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a77995: Add CAN FD supportUlrich Hecht2017-11-281-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds CAN FD controller node for r8a77995. Based on a patch for r8a7796 by Chris Paterson. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a77995: Add CAN supportUlrich Hecht2017-11-281-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds CAN controller nodes for r8a77995. Based on a patch for r8a7796 by Chris Paterson. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a77995: Add CAN external clock supportUlrich Hecht2017-11-281-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds external CAN clock node for r8a77995. This clock can be used as fCAN clock of CAN and CAN FD controller. Based on a patch for r8a7796 by Chris Paterson. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a7795-salvator-xs: Add SoC name to file headerGeert Uytterhoeven2017-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Document clearly which SoC this DTS applies to, to distinguish from Salvator-XS boards equipped with other SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a7796-salvator-x: Add SoC name to file headerGeert Uytterhoeven2017-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Document clearly which SoC this DTS applies to, to distinguish from Salvator-X boards equipped with other SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a7795-salvator-x: Add SoC name to file headerGeert Uytterhoeven2017-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Document clearly which SoC this DTS applies to, to distinguish from Salvator-X boards equipped with other SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a7795-es1-salvator-x: Add SoC name to file headerGeert Uytterhoeven2017-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Document clearly which SoC this DTS applies to, to distinguish from Salvator-X boards equipped with other SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: salvator-common: Add BD9571 PMICGeert Uytterhoeven2017-11-281-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device node for the ROHM BD9571MWV PMIC. This was based on the example in the DT binding documentation, but using IRQ0 instead of a GPIO interrupt, as that matches the schematics, and because INTC-EX is a simpler block. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | arm64: dts: renesas: r8a7795: Enable IPMMU-VI0, VP1, DS0, DS1 and MMMagnus Damm2017-11-281-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the r8a7795 device nodes for IPMMU-VI0, IPMMU-VP1, IPMMU-DS0, IPMMU-DS1 and the shared IPMMU-MM device. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a7795-es1: Enable IPMMU-MP1Magnus Damm2017-11-281-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Enable the r8a7795 ES1.x device node for IPMMU-MP1. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a7795: Connect SATA to IPMMU-HCMagnus Damm2017-11-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add IPMMU-HC to the SATA device node. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a7795: Connect Ethernet-AVB to IPMMU-DS0Magnus Damm2017-11-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add IPMMU-DS0 to the Ethernet-AVB device node. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a7795-es1: Point VSPI via FCPVI to IPMMU-VPMagnus Damm2017-11-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Hook up the FCPVI devices to allow use of VSPI with IPMMU-VP. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a7795: Point VSPI via FCPVI to IPMMU-VP0/1Magnus Damm2017-11-282-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Hook up the FCPVI devices to allow use of VSPI with IPMMU-VP0 and IPMMU-VP1. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a7795: Point VSPBC/VSPBD via FCPVB to IPMMU-VP0/1Magnus Damm2017-11-282-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Hook up the FCPVB devices to allow use of VSPBC/VSPBD with IPMMU-VP0 and IPMMU-VP1. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a7795-es1: Point FDP1 via FCPF to IPMMU-VP0Magnus Damm2017-11-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Hook up the FCPF devices to allow use of FDP1 with IPMMU-VP0. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a7795: Point FDP1 via FCPF to IPMMU-VP0/1Magnus Damm2017-11-282-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Hook up the FCPF devices to allow use of FDP1 with IPMMU-VP. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | arm64: dts: renesas: r8a7795-es1: Point DU/VSPD via FCPVD to IPMMU-VI0Magnus Damm2017-11-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Hook up the FCPVD devices to allow use of the VSP and DU together with IPMMU-VI0. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-19 15:16:33 +0000