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* drm/amd/display: Wake DMCUB before executing GPINT commandsNicholas Kazlauskas2023-12-194-54/+77
| | | | | | | | | | | | | | | | | | | | | | | | [Why] DMCUB can be in idle when we attempt to interface with the HW through the GPINT mailbox resulting in a system hang. [How] Add dc_wake_and_execute_gpint() to wrap the wake, execute, sleep sequence. If the GPINT executes successfully then DMCUB will be put back into sleep after the optional response is returned. It functions similar to the inbox command interface. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Wake DMCUB before sending a commandNicholas Kazlauskas2023-12-1925-63/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] We can hang in place trying to send commands when the DMCUB isn't powered on. [How] For functions that execute within a DC context or DC lock we can wrap the direct calls to dm_execute_dmub_cmd/list with code that exits idle power optimizations and reallows once we're done with the command submission on success. For DM direct submissions the DM will need to manage the enter/exit sequencing manually. We cannot invoke a DMCUB command directly within the DM execution helper or we can deadlock. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Refactor DMCUB enter/exit idle interfaceNicholas Kazlauskas2023-12-194-12/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] We can hang in place trying to send commands when the DMCUB isn't powered on. [How] We need to exit out of the idle state prior to sending a command, but the process that performs the exit also invokes a command itself. Fixing this issue involves the following: 1. Using a software state to track whether or not we need to start the process to exit idle or notify idle. It's possible for the hardware to have exited an idle state without driver knowledge, but entering one is always restricted to a driver allow - which makes the SW state vs HW state mismatch issue purely one of optimization, which should seldomly be hit, if at all. 2. Refactor any instances of exit/notify idle to use a single wrapper that maintains this SW state. This works simialr to dc_allow_idle_optimizations, but works at the DMCUB level and makes sure the state is marked prior to any notify/exit idle so we don't enter an infinite loop. 3. Make sure we exit out of idle prior to sending any commands or waiting for DMCUB idle. This patch takes care of 1/2. A future patch will take care of wrapping DMCUB command submission with calls to this new interface. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix usb-c connector_typeAllen Pan2023-12-191-0/+5
| | | | | | | | | | | | | [why] BIOS switches to use USB-C connector type 0x18, but VBIOS's objectInfo table not supported yet. driver needs to patch it based on enc_cap from system integration info table. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Allen Pan <allen.pan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add debug option for ExtendedVBlank DLG adjustMuhammad Ahmed2023-12-192-1/+3
| | | | | | | | | | | [why & how] Add new option for debug usage Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Set test_pattern_changed update flag on pipe enableGeorge Shen2023-12-191-0/+4
| | | | | | | | | | | | | | | | | [Why] In certain cases, ODM pipe split can occur while stream already has test pattern enabled. The new pipe used in the ODM combine config must be configured to output the test pattern in this case. [How] If the stream is configured to output test pattern, then set the test_pattern_changed update flag for the new pipe when it gets enabled. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: dereference variable before checking for zeroJosip Pavic2023-12-191-1/+1
| | | | | | | | | | | | | | | [Why] Driver incorrectly checks if pointer variable OutBpp is null instead of if the value being pointed to is zero. [How] Dereference OutBpp before checking for a value of zero. Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Josip Pavic <josip.pavic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: get dprefclk ss info from integration info tableCharlene Liu2023-12-192-5/+16
| | | | | | | | | | | | | | | | [why & how] we have two SSC_En: we get ssc_info from dce_info for MPLL_SSC_EN. we used to call VBIOS cmdtbl's smu_info's SS persentage for DPRECLK SS info, is used for DP AUDIO and VBIOS' smu_info table was from systemIntegrationInfoTable. since dcn35 VBIOS removed smu_info, driver need to use integrationInfotable directly. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: skip error logging when DMUB is inactive from S3Samson Tam2023-12-193-12/+27
| | | | | | | | | | | | | | | | [Why] On resume from S3, while DMUB is inactive, DMUB queue and execute calls will not work. Skip reporting errors in these scenarios [How] Add new return code during DMUB queue and execute calls when DMUB is in S3 state. Skip logging errors in these scenarios Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdkfd: Use partial hmm page walk during buffer validation in SVMXiaogang Chen2023-12-192-66/+48
| | | | | | | | | | | SVM uses hmm page walk to valid buffer before map to gpu vm. After have partial migration/mapping do validation on same vm range as migration/map do instead of whole svm range that can be very large. This change is expected to improve svm code performance. Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd: Add missing definitions for `SMU_MAX_LEVELS_VDDGFX`Mario Limonciello2023-12-192-0/+2
| | | | | | | | | | | | | | It is reported that on a Topaz dGPU the kernel emits: amdgpu: can't get the mac of 5 This is because there is no definition for max levels of VDDGFX declared for SMU71 or SMU7. The correct definition is VDDC so use this. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3049 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Documentation/amdgpu: Remove a spurious characterMario Limonciello2023-12-191-1/+1
| | | | | | | | `/` wasn't meant to be in the Dragon Range line Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Documentation/amdgpu: Add Hawk Point processorsMario Limonciello2023-12-191-1/+2
| | | | | | | | | These have been announced so add them to the table. Link: https://www.amd.com/en/product/13971 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: make flip_timestamp_in_us a 64-bit variableJosip Pavic2023-12-191-1/+1
| | | | | | | | | | | | | | | | [Why] This variable currently overflows after about 71 minutes. This doesn't cause any known functional issues but it does make debugging more difficult. [How] Make it a 64-bit variable. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Josip Pavic <josip.pavic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add case for dcn35 to support usb4 dmub hpd eventWayne Lin2023-12-191-8/+18
| | | | | | | | | | | | [Why & how] Refactor dc_is_dmub_outbox_supported() a bit and add case for dcn35 to register dmub outbox notification irq to handle usb4 relevant hpd event. Reviewed-by: Roman Li <roman.li@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: disable FPO and SubVP for older DMUB versions on DCN32xHamza Mahfooz2023-12-191-0/+6
| | | | | | | | | | | | | | | | | There have recently been changes that break backwards compatibility, that were introduced into DMUB firmware (for DCN32x) concerning FPO and SubVP. So, since those are just power optimization features, we can just disable them unless the user is using a new enough version of DMUB firmware. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2870 Fixes: ed6e2782e974 ("drm/amd/display: For cursor P-State allow for SubVP") Reported-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Closes: https://lore.kernel.org/r/CABXGCsNRb0QbF2pKLJMDhVOKxyGD6-E+8p-4QO6FOWa6zp22_A@mail.gmail.com/ Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add a new DC debug mask for PSR-SUMario Limonciello2023-12-192-0/+4
| | | | | | | | | | | | Some issues have been raised that appear to be tied to PSR-SU. To allow users to confirm they're tied to PSR-SU without turning off PSR entirely introduce a new debug mask: amdgpu.dcdebugmask=0x200 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add function for dumping clk registersJohnson Chen2023-12-192-4/+22
| | | | | | | | | | | | | | [why] Allow devs to check raw clk register values by dumping them on the log [how] Add clk register dump implementation Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Johnson Chen <johnson.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Unify optimize_required flags and VRR adjustmentsAric Cyr2023-12-195-17/+10
| | | | | | | | | | | | | | | | | | | [why] There is only a single call to dc_post_update_surfaces_to_stream so there is no need to have two flags to control it. Unifying this to a single flag allows dc_stream_adjust_vmin_vmax to skip actual programming when there is no change required. [how] Remove wm_optimze_required flag and set only optimize_required in its place. Then in dc_stream_adjust_vmin_vmax, check that the stream timing range matches the requested one and skip programming if they are equal. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Revert " drm/amd/display: Use channel_width = 2 for vram ↵Alvin Lee2023-12-151-7/+1
| | | | | | | | | | | | | | table 3.0" [Description] Revert commit fec05adc40c2 ("drm/amd/display: Use channel_width = 2 for vram table 3.0") Because the issue is being fixed from VBIOS side. Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: remove HPO PG in driver sideMuhammad Ahmed2023-12-151-0/+1
| | | | | | | | | | | [why & how] Add config to make HPO PG handled in dmubfw ips entry/exit Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: do not send commands to DMUB if DMUB is inactive from S3Samson Tam2023-12-155-0/+55
| | | | | | | | | | | | | | | | | [Why] On resume from S3, may get apply_idle_optimizations call while DMUB is inactive which will just time out. [How] Set and track power state in dmub_srv and check power state before sending commands to DMUB. Add interface in both dmub_srv and dc_dmub_srv Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/swsmu: remove duplicate definition of smu v14_0_0 driver if versionLi Ma2023-12-152-6/+1
| | | | | | | | | | There is a repeated define of smu v14_0_0 driver if version, so delete one in driver if header. Signed-off-by: Li Ma <li.ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: make an improvement on amdgpu_hmm_range_get_pagesJames Zhu2023-12-151-1/+1
| | | | | | | | Only schedule when hmm_range_fault returns error. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: increase hmm range get pages timeoutJames Zhu2023-12-151-2/+2
| | | | | | | | | | | When application tries to allocate all system memory and cause memory to swap out. Needs more time for hmm_range_fault to validate the remaining page for allocation. To be safe, increase timeout value to 1 second for 64MB range. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdkfd: svm range always mapped flag not working on APUPhilip Yang2023-12-151-6/+12
| | | | | | | | | | | | | | | | | | | | | On gfx943 APU there is no VRAM and page migration, queue CWSR area, svm range with always mapped flag, is not mapped to GPU correctly. This works fine if retry fault on CWSR area can be recovered, but could cause deadlock if there is another retry fault recover waiting for CWSR to finish. Fix this by mapping svm range with always mapped flag to GPU with ACCESS attribute if XNACK ON. There is side effect, because all GPUs have ACCESS attribute by default on new svm range with XNACK on, the CWSR area will be mapped to all GPUs after this change. This side effect will be fixed with Thunk change to set CWSR svm range with ACCESS_IN_PLACE attribute on the GPU that user queue is created. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdkfd: only flush mes process context if mes support is thereJonathan Kim2023-12-151-1/+2
| | | | | | | | | | | Fix up on mes process context flush to prevent non-mes devices from spamming error messages or running into undefined behaviour during process termination. Fixes: bd33bb1409b4 ("drm/amdkfd: fix mes set shader debugger process management") Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Eric Huang <jinhuieric.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix documentation for dm_crtc_additional_color_mgmt()Melissa Wen2023-12-141-1/+1
| | | | | | | | | | warning: expecting prototype for drm_crtc_additional_color_mgmt(). Prototype was for dm_crtc_additional_color_mgmt() instead Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312141801.o9eBCxt9-lkp@intel.com/ Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix documentation for amdgpu_dm_verify_lut3d_size()Alex Deucher2023-12-141-1/+1
| | | | | | | | | | | It takes the plane state rather than the crtc state. Fixes: aba8b76baabd ("drm/amd/display: add plane shaper LUT support") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Melissa Wen <mwen@igalia.com> Cc: Harry.Wentland@amd.com
* drm/amd/pm: fix a double-free in amdgpu_parse_extended_power_tableZhipeng Lu2023-12-141-39/+13
| | | | | | | | | | | | | | | | | | | | | | | | The amdgpu_free_extended_power_table is called in every error-handling paths of amdgpu_parse_extended_power_table. However, after the following call chain of returning: amdgpu_parse_extended_power_table |-> kv_dpm_init / si_dpm_init (the only two caller of amdgpu_parse_extended_power_table) |-> kv_dpm_sw_init / si_dpm_sw_init (the only caller of kv_dpm_init / si_dpm_init, accordingly) |-> kv_dpm_fini / si_dpm_fini (goto dpm_failed in xx_dpm_sw_init) |-> amdgpu_free_extended_power_table As above, the amdgpu_free_extended_power_table is called twice in this returning chain and thus a double-free is triggered. Similarily, the last kfree in amdgpu_parse_extended_power_table also cause a double free with amdgpu_free_extended_power_table in kv_dpm_fini. Fixes: 84176663e70d ("drm/amd/pm: create a new holder for those APIs used only by legacy ASICs(si/kv)") Signed-off-by: Zhipeng Lu <alexious@zju.edu.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* gpu/drm/radeon: fix two memleaks in radeon_vm_initZhipeng Lu2023-12-141-2/+6
| | | | | | | | | | When radeon_bo_create and radeon_vm_clear_bo fail, the vm->page_tables allocated before need to be freed. However, neither radeon_vm_init itself nor its caller have done such deallocation. Fixes: 6d2f2944e95e ("drm/radeon: use normal BOs for the page tables v4") Signed-off-by: Zhipeng Lu <alexious@zju.edu.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drivers/amd/pm: fix a use-after-free in kv_parse_power_tableZhipeng Lu2023-12-141-3/+1
| | | | | | | | | | | | | | | | | | When ps allocated by kzalloc equals to NULL, kv_parse_power_table frees adev->pm.dpm.ps that allocated before. However, after the control flow goes through the following call chains: kv_parse_power_table |-> kv_dpm_init |-> kv_dpm_sw_init |-> kv_dpm_fini The adev->pm.dpm.ps is used in the for loop of kv_dpm_fini after its first free in kv_parse_power_table and causes a use-after-free bug. Fixes: a2e73f56fa62 ("drm/amdgpu: Add support for CIK parts") Signed-off-by: Zhipeng Lu <alexious@zju.edu.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: fix a double-free in si_dpm_initZhipeng Lu2023-12-141-3/+2
| | | | | | | | | | | | | | When the allocation of adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries fails, amdgpu_free_extended_power_table is called to free some fields of adev. However, when the control flow returns to si_dpm_sw_init, it goes to label dpm_failed and calls si_dpm_fini, which calls amdgpu_free_extended_power_table again and free those fields again. Thus a double-free is triggered. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Signed-off-by: Zhipeng Lu <alexious@zju.edu.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: Remove unneeded semicolonYang Li2023-12-141-1/+1
| | | | | | | | | ./drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c:1418:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=7743 Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/debugfs: fix error code when smc register accessors are NULLAlex Deucher2023-12-141-2/+2
| | | | | | | | Should be -EOPNOTSUPP. Fixes: 5104fdf50d32 ("drm/amdgpu: Fix a null pointer access when the smc_rreg pointer is NULL") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add 3x4 CTM support for plane CTMJoshua Ashton2023-12-143-4/+34
| | | | | | | | | | | | Create drm_color_ctm_3x4 to support 3x4-dimension plane CTM matrix and convert DRM CTM to DC CSC float matrix. v3: - rename ctm2 to ctm_3x4 (Harry) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add plane CTM supportMelissa Wen2023-12-142-0/+27
| | | | | | | | | | | | | Map the plane CTM driver-specific property to DC plane, instead of DC stream. The remaining steps to program DPP block are already implemented on DC shared-code. v3: - fix comment about plane and CRTC CTMs priorities (Harry) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: add power save mode workload for smu 13.0.10Kenneth Feng2023-12-141-10/+13
| | | | | | | | | add power save mode workload for smu 13.0.10, so that in compute mode, pmfw will add margin since some applications requres higher margin. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/vpe: enable vpe dpmPeyton Lee2023-12-143-0/+276
| | | | | | | | enable vpe dpm Signed-off-by: Peyton Lee <peytolee@amd.com> Reviewed-by: Lang Yu <lang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add plane CTM driver-specific propertyMelissa Wen2023-12-144-0/+37
| | | | | | | | | | | Plane CTM for pre-blending color space conversion. Only enable driver-specific plane CTM property on drivers that support both pre- and post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it conflits with DRM CRTC CTM property. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: copy 3D LUT settings from crtc state to stream_updateJoshua Ashton2023-12-141-0/+4
| | | | | | | | | | | When commiting planes, we copy color mgmt resources to the stream state. Do the same for shaper and 3D LUTs. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Co-developed-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pm: support return vpe clock tablePeyton Lee2023-12-144-0/+33
| | | | | | | | pm supports return vpe clock table and soc clock table Signed-off-by: Peyton Lee <peytolee@amd.com> Reviewed-by: Li Ma <li.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fix ftrace event amdgpu_bo_move always move on same heapWang, Beyond2023-12-143-17/+5
| | | | | | | | | | | | | | | Issue: during evict or validate happened on amdgpu_bo, the 'from' and 'to' is always same in ftrace event of amdgpu_bo_move where calling the 'trace_amdgpu_bo_move', the comment says move_notify is called before move happens, but actually it is called after move happens, here the new_mem is same as bo->resource Fix: move trace_amdgpu_bo_move from move_notify to amdgpu_bo_move Signed-off-by: Wang, Beyond <Wang.Beyond@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: allow newer DC hardware to use degamma ROM for PQ/HLGJoshua Ashton2023-12-141-11/+18
| | | | | | | | | | | | | | | | | Need to funnel the color caps through to these functions so it can check that the hardware is capable. v2: - remove redundant color caps assignment on plane degamma map (Harry) - pass color caps to degamma params v3: - remove unused color_caps parameter from set_color_properties (Harry) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add plane blend LUT and TF supportJoshua Ashton2023-12-142-4/+53
| | | | | | | | | | | | | | | | Map plane blend properties to DPP blend gamma. Plane blend is a post-3D LUT curve that linearizes color space for blending. It may be defined by a user-blob LUT and/or predefined transfer function. As hardcoded curve (ROM) is not supported on blend gamma, we use AMD color module to fill parameters when setting non-linear TF with empty LUT. v2: - rename DRM TFs to AMDGPU TFs Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: handle empty LUTs in __set_input_tfJoshua Ashton2023-12-141-8/+12
| | | | | | | | | | | | Unlike degamma, blend gamma doesn't support hardcoded curve (predefined/ROM), but we can use AMD color module to fill blend gamma parameters when we have non-linear plane gamma TF without plane gamma LUT. The regular degamma path doesn't hit this. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add plane 3D LUT supportMelissa Wen2023-12-142-4/+99
| | | | | | | | | | | | | | | | | | | | | | Wire up DC 3D LUT to DM plane color management (pre-blending). On AMD display HW, 3D LUT comes after a shaper curve and we always have to program a shaper curve to delinearize or normalize the color space before applying a 3D LUT (since we have a reduced number of LUT entries). In this version, the default values of 3D LUT for size and bit_depth are 17x17x17 and 12-bit, but we already provide here a more generic mechanisms to program other supported values (9x9x9 size and 10-bit). v2: - started with plane 3D LUT instead of CRTC 3D LUT support v4: - lut3d_size is the max dimension size instead of # of entries Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: warn when there are still mappings when a BO is destroyed v2Christian König2023-12-131-0/+2
| | | | | | | | | | This can only happen when there is a reference counting bug. v2: fix typo Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Prevent multiple debug error lines on suspendWoody Suwalski2023-12-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Fix to avoid multiple debug error lines printed on every suspend by Radeon driver's debugfs. radeon_debugfs_init() calls debugfs_create_file() for every ring. This results in printing multiple error lines to the screen and dmesg similar to this: [   92.378726] debugfs: File 'radeon_ring_gfx' in directory '0000:00:01.0' already present! [   92.378732] debugfs: File 'radeon_ring_cp1' in directory '0000:00:01.0' already present! [   92.378734] debugfs: File 'radeon_ring_cp2' in directory '0000:00:01.0' already present! [   92.378737] debugfs: File 'radeon_ring_dma1' in directory '0000:00:01.0' already present! [   92.378739] debugfs: File 'radeon_ring_dma2' in directory '0000:00:01.0' already present! [   92.380775] debugfs: File 'radeon_ring_uvd' in directory '0000:00:01.0' already present! [   92.406620] debugfs: File 'radeon_ring_vce1' in directory '0000:00:01.0' already present! [   92.406624] debugfs: File 'radeon_ring_vce2' in directory '0000:00:01.0' already present! Patch v1: The fix was to run lookup() for the file before trying to (re)create that debug file. Patch v2: Call the radeon_debugfs_init() only once when radeon ring is initialized (as suggested by Christian K. - thanks) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Woody Suwalski <terraluna977@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add plane shaper TF supportMelissa Wen2023-12-131-4/+11
| | | | | | | | | | | Enable usage of predefined transfer func in addition to shaper 1D LUT. That means we can save some complexity by just setting a predefined curve, instead of programming a custom curve when preparing color space for applying 3D LUT. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-16 11:19:34 +0000