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* Merge tag 'pinctrl-v6.11-1' of ↵Linus Torvalds13 days11-289/+1328
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Some new drivers is the main part, the rest is cleanups and nonurgent fixes. Nothing much special about this, no core changes this time. New drivers: - Renesas RZ/V2H(P) SoC - NXP Freescale i.MX91 SoC - Nuvoton MA35D1 SoC - Qualcomm PMC8380, SM4250, SM4250 LPI Enhancements: - A slew of scoped-based simplifications of of_node_put()" * tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits) pinctrl: renesas: rzg2l: Support output enable on RZ/G2L pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions pinctrl: renesas: rzg2l: Clarify OEN read/write support dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties pinctrl: freescale: Use scope based of_node_put() cleanups pinctrl: equilibrium: Use scope based of_node_put() cleanups pinctrl: ti: iodelay: Use scope based of_node_put() cleanups pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32 pinctrl: cy8c95x0: Update cache modification pinctrl: cy8c95x0: Use cleanup.h pinctrl: renesas: r8a779h0: Remove unneeded separators pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function pinctrl: renesas: r8a779g0: Remove unneeded separators pinctrl: renesas: r8a779h0: Add AVB MII pins and groups pinctrl: renesas: r8a779g0: Fix TPU suffixes pinctrl: renesas: r8a779g0: Fix TCLK suffixes pinctrl: renesas: r8a779g0: FIX PWM suffixes pinctrl: renesas: r8a779g0: Fix IRQ suffixes ...
| * dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range descriptionNishanth Menon2024-07-031-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The binding is supposed to describe the properties of each element of the pinctrl-single,gpio-range array entry, however when we use "- items:" instead of "items:", it explicitly describes that there is just a single entry in the array. The pinctrl-single,gpio-range property should describe more than one entry in the array. Fix the typo and adjust the alignment of the description of the entries appropriately. Fixes: 677a62482bd6 ("dt-bindings: pinctrl: Update pinctrl-single to use yaml") Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/20240627150610.469645-1-nm@ti.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: npcm8xx: add missing pin group and mux functionTomer Maimon2024-07-031-10/+12
| | | | | | | | | | | | | | | | | | | | | | Add the following missing pin group and mux function: smb6b, smb6c, smb6d, smb7b, smb7c, smb7d, bu4, bu4b, bu5, bu5b, bu6, gpo187. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/20240630090104.565779-1-tmaimon77@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: pinctrl-single: fix schmitt related propertiesInochi Amaoto2024-07-031-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "pinctrl-single,input-schmitt" have four arguments in the bindings but the driver needs two. According to the meaning of other properties and driver, it should have "enable" suffix. Fortunately, there is no dts using this property, so it is safe to correct this property with the right name. Rename existed property "pinctrl-single,input-schmitt" to "pinctrl-single,input-schmitt-enable" and add the right description for property "pinctrl-single,input-schmitt" used by the driver. Fixes: 677a62482bd6 ("dt-bindings: pinctrl: Update pinctrl-single to use yaml") Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/IA1PR20MB4953D5E7D7D68DDCE31C0031BBCF2@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: aspeed,ast2600-pinctrl: add NCSI groupsPotin Lai2024-06-261-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In the NCSI pin table, the reference clock output pin (RMIIXRCLKO) is not needed on the management controller side. Add "NCSI" pin groups that are equivalent to the RMII pin groups, but without the RMIIXRCLKO pin. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/20240621093142.698529-2-potin.lai.pt@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: qcom: Add SM4250 pinctrlSrinivas Kandagatla2024-06-261-0/+118
| | | | | | | | | | | | | | | | | | | | Add device tree binding Documentation details for Qualcomm SM4250 LPASS LPI(Low power Island) pinctrl device. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-1-a0342e47e21b@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: xilinx: Add support for function with pinsSean Anderson2024-06-171-169/+180
| | | | | | | | | | | | | | | | | | | | | | Support specifying the function per-pin. The driver doesn't care whether you use pins or groups for this purpose. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20240610223550.2449230-2-sean.anderson@linux.dev Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Describe I3C, USBAndrew Jeffery2024-06-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I3C1 and I3C2 become muxed functions in the mass production release of the AST2600. Also document the USB2A device and USB2B HID mux options. Squash warnings such as: arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dtb: pinctrl: usb2ad_default:function:0: 'USB2AD' is not one of ['ADC0', 'ADC1', 'ADC10', 'ADC11', 'ADC12', 'ADC13', 'ADC14', 'ADC15', 'ADC2', 'ADC3', 'ADC4', 'ADC5', 'ADC6', 'ADC7', 'ADC8', 'ADC9', 'BMCINT', 'EMMC', 'ESPI', 'ESPIALT', 'FSI1', 'FSI2', 'FWQSPI', 'FWSPIABR', 'FWSPID', 'FWSPIWP', 'GPIT0', 'GPIT1', 'GPIT2', 'GPIT3', 'GPIT4', 'GPIT5', 'GPIT6', 'GPIT7', 'GPIU0', 'GPIU1', 'GPIU2', 'GPIU3', 'GPIU4', 'GPIU5', 'GPIU6', 'GPIU7', 'I2C1', 'I2C10', 'I2C11', 'I2C12', 'I2C13', 'I2C14', 'I2C15', 'I2C16', 'I2C2', 'I2C3', 'I2C4', 'I2C5', 'I2C6', 'I2C7', 'I2C8', 'I2C9', 'I3C3', 'I3C4', 'I3C5', 'I3C6', 'JTAGM', 'LHPD', 'LHSIRQ', 'LPC', 'LPCHC', 'LPCPD', 'LPCPME', 'LPCSMI', 'LSIRQ', 'MACLINK1', 'MACLINK2', 'MACLINK3', 'MACLINK4', 'MDIO1', 'MDIO2', 'MDIO3', 'MDIO4', 'NCTS1', 'NCTS2', 'NCTS3', 'NCTS4', 'NDCD1', 'NDCD2', 'NDCD3', 'NDCD4', 'NDSR1', 'NDSR2', 'NDSR3', 'NDSR4', 'NDTR1', 'NDTR2', 'NDTR3', 'NDTR4', 'NRI1', 'NRI2', 'NRI3', 'NR I4', 'NRTS1', 'NRTS2', 'NRTS3', 'NRTS4', 'OSCCLK', 'PEWAKE', 'PWM0', 'PWM1', 'PWM10', 'PWM11', 'PWM12', 'PWM13', 'PWM14', 'PWM15', 'PWM2', 'PWM3', 'PWM4', 'PWM5', 'PWM6', 'PWM7', 'PWM8', 'PWM9', 'RGMII1', 'RGMII2', 'RGMII3', 'RGMII4', 'RMII1', 'RMII2', 'RMII3', 'RMII4', 'RXD1', 'RXD2', 'RXD3', 'RXD4', 'SALT1', 'SALT10', 'SALT11', 'SALT12', 'SALT13', 'SALT14', 'SALT15', 'SALT16', 'SALT2', 'SALT3', 'SALT4', 'SALT5', 'SALT6', 'SALT7', 'SALT8', 'SALT9', 'SD1', 'SD2', 'SGPM1', 'SGPM2', 'SGPS1', 'SGPS2', 'SIOONCTRL', 'SIOPBI', 'SIOPBO', 'SIOPWREQ', 'SIOPWRGD', 'SIOS3', 'SIOS5', 'SIOSCI', 'SPI1', 'SPI1ABR', 'SPI1CS1', 'SPI1WP', 'SPI2', 'SPI2CS1', 'SPI2CS2', 'TACH0', 'TACH1', 'TACH10', 'TACH11', 'TACH12', 'TACH13', 'TACH14', 'TACH15', 'TACH2', 'TACH3', 'TACH4', 'TACH5', 'TACH6', 'TACH7', 'TACH8', 'TACH9', 'THRU0', 'THRU1', 'THRU2', 'THRU3', 'TXD1', 'TXD2', 'TXD3', 'TXD4', 'UART10', 'UART11', 'UART12', 'UART13', 'UART6', 'UART7', 'UART8', 'UART9', 'USBAD', 'USBADP', 'USB2AH', 'USB2AHP', 'USB 2BD', 'USB2BH', 'VB', 'VGAHS', 'VGAVS', 'WDTRST1', 'WDTRST2', 'WDTRST3', 'WDTRST4'] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240531-dt-warnings-gpio-ast2600-pinctrl-funcs-groups-v1-3-a6fe2281a1b8@codeconstruct.com.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: aspeed,ast2500-pinctrl: Describe SGPMAndrew Jeffery2024-06-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Squash warnings such as: arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dtb: pinctrl@80: sgpm_default:groups:0: 'SGPM' is not one of ['ACPI', 'ADC0', 'ADC1', 'ADC10', 'ADC11', 'ADC12', 'ADC13', 'ADC14', 'ADC15', 'ADC2', 'ADC3', 'ADC4', 'ADC5', 'ADC6', 'ADC7', 'ADC8', 'ADC9', 'BMCINT', 'DDCCLK', 'DDCDAT', 'ESPI', 'FWSPICS1', 'FWSPICS2', 'GPID0', 'GPID2', 'GPID4', 'GPID6', 'GPIE0', 'GPIE2', 'GPIE4', 'GPIE6', 'I2C10', 'I2C11', 'I2C12', 'I2C13', 'I2C14', 'I2C3', 'I2C4', 'I2C5', 'I2C6', 'I2C7', 'I2C8', 'I2C9', 'LAD0', 'LAD1', 'LAD2', 'LAD3', 'LCLK', 'LFRAME', 'LPCHC', 'LPCPD', 'LPCPLUS', 'LPCPME', 'LPCRST', 'LPCSMI', 'LSIRQ', 'MAC1LINK', 'MAC2LINK', 'MDIO1', 'MDIO2', 'NCTS1', 'NCTS2', 'NCTS3', 'NCTS4', 'NDCD1', 'NDCD2', 'NDCD3', 'NDCD4', 'NDSR1', 'NDSR2', 'NDSR3', 'NDSR4', 'NDTR1', 'NDTR2', 'NDTR3', 'NDTR4', 'NRI1', 'NRI2', 'NRI3', 'NRI4', 'NRTS1', 'NRTS2', 'NRTS3', 'NRTS4', 'OSCCLK', 'PEWAKE', 'PNOR', 'PWM0', 'PWM1', 'PWM2', 'PWM3', 'PWM4', 'PWM5', 'PWM6', 'PWM7', 'RGMII1', 'RGMII2', 'RMII1', 'RMII2', 'RXD1', ' RXD2', 'RXD3', 'RXD4', 'SALT1', 'SALT10', 'SALT11', 'SALT12', 'SALT13', 'SALT14', 'SALT2', 'SALT3', 'SALT4', 'SALT5', 'SALT6', 'SALT7', 'SALT8', 'SALT9', 'SCL1', 'SCL2', 'SD1', 'SD2', 'SDA1', 'SDA2', 'SGPS1', 'SGPS2', 'SIOONCTRL', 'SIOPBI', 'SIOPBO', 'SIOPWREQ', 'SIOPWRGD', 'SIOS3', 'SIOS5', 'SIOSCI', 'SPI1', 'SPI1CS1', 'SPI1DEBUG', 'SPI1PASSTHRU', 'SPI2CK', 'SPI2CS0', 'SPI2CS1', 'SPI2MISO', 'SPI2MOSI', 'TIMER3', 'TIMER4', 'TIMER5', 'TIMER6', 'TIMER7', 'TIMER8', 'TXD1', 'TXD2', 'TXD3', 'TXD4', 'UART6', 'USB11BHID', 'USB2AD', 'USB2AH', 'USB2BD', 'USB2BH', 'USBCKI', 'VGABIOSROM', 'VGAHS', 'VGAVS', 'VPI24', 'VPO', 'WDTRST1', 'WDTRST2'] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240531-dt-warnings-gpio-ast2600-pinctrl-funcs-groups-v1-2-a6fe2281a1b8@codeconstruct.com.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: aspeed: Use block syntax for function and groupsAndrew Jeffery2024-06-173-83/+774
| | | | | | | | | | | | | | | | | | | | | | The expansion makes the documents a lot longer, but it's easier to review changes to functions and groups when we're not having to deal with line wrapping. Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240531-dt-warnings-gpio-ast2600-pinctrl-funcs-groups-v1-1-a6fe2281a1b8@codeconstruct.com.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'renesas-pinctrl-for-v6.11-tag1' of ↵Linus Walleij2024-06-171-19/+33
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.11 - Add support for the new RZ/V2H(P) (R9A09G057) Soc, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoCLad Prabhakar2024-06-111-4/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add documentation for the pin controller found on the Renesas RZ/V2H(P) (R9A09G057) SoC. The RZ/V2H PFC varies slightly compared to the RZ/G2L family: - Additional bits need to be set during pinmuxing, - The GPIO pin count is different. Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is added for the RZ/V2H(P) SoC. Also, add the 'renesas,output-impedance' property. The drive strength settings on RZ/V2H(P) depend on the different power rails coming out from the PMIC (connected via I2C). These power rails (required for drive strength) can be 1.2V, 1.8V, or 3.3V. Pins are grouped into 4 groups: Group 1: Impedance - 150/75/38/25 ohms (at 3.3V) - 130/65/33/22 ohms (at 1.8V) Group 2: Impedance - 50/40/33/25 ohms (at 1.8V) Group 3: Impedance - 150/75/37.5/25 ohms (at 3.3V) - 130/65/33/22 ohms (at 1.8V) Group 4: Impedance - 110/55/30/20 ohms (at 1.8V) - 150/75/38/25 ohms (at 1.2V) The 'renesas,output-impedance' property, as documented, can be [0, 1, 2, 3], these correspond to register bit values that can be set in the PFC_IOLH_mn register, which adjusts the drive strength value and is pin-dependent. As power rail information may not be available very early in the boot process, the 'renesas,output-impedance' property is added instead of reusing the 'output-impedance-ohms' property. Also, allow bias-disable, bias-pull-down and bias-pull-up properties as these can be used to configure the pins. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240606085133.632307-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the objectLad Prabhakar2024-05-281-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the bogus check from object as this didn't really add restriction check. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240423175900.702640-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | dt-bindings: pinctrl: qcom,pmic-gpio: Document PMC8380Konrad Dybcio2024-06-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | PMC8380 is a new PMIC used with X1 SoCs. Document it Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240525-topic-pmc8380_gpio-v2-1-2de50cb28ac1@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | dt-bindings: pinctrl: Document nuvoton ma35d1 pin controlJacky Huang2024-06-171-0/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add documentation to describe nuvoton ma35d1 pin control and GPIO. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240521012447.42211-3-ychuang570808@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | dt-bindings: pinctrl: imx: Support i.MX91 IOMUXCPeng Fan2024-06-171-3/+5
| |/ | | | | | | | | | | | | | | | | | | | | i.MX91 and i.MX93 share similar design. They could share same dt-binding doc, so rename fsl,imx93-pinctrl.yaml to fsl,imx9-pinctrl.yaml and add i.MX91 compatible string Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240513-imx91-pinctrl-v1-1-c99a23c6843a@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* / dt-bindings: pinctrl: qcom,pmic-gpio: drop pm8008Johan Hovold2024-06-171-3/+0
|/ | | | | | | | | | | | | | | | The binding for PM8008 is being reworked so that internal details like interrupts and register offsets are no longer described. This specifically also involves dropping the gpio child node and its compatible string which is no longer needed. Note that there are currently no users of the upstream binding and driver. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240529162958.18081-10-johan+linaro@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'samsung-pinctrl-6.10' of ↵Linus Walleij2024-05-061-0/+21
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.10 1. Add support for toggling bus clock (PCLK) for any pin controller register accesses. This looks needed on newer Samsung chips, like Google GS101 and probably Exynos850. 2. Drop old, deprecated in v6.1 bindings header with register constants. The constants were moved to DTS headers. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: samsung: google,gs101-pinctrl needs a clockAndré Draszik2024-04-291-0/+21
| | | | | | | | | | | | | | | | | | The pin controller on Google Tensor gs101 requires a bus clock for register access to work. Add it. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20240426-samsung-pinctrl-busclock-v3-1-adb8664b8a7e@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
* | dt-bindings: pinctrl: qcom,pmic-gpio: Fix "comptaible" typo for PMIH0108Anjelique Melendez2024-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | Fix "comptaible" typo in if schema for qcom,pmih0108-gpio. Fixes: 6acc46f8c065 ("dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIH0108 and PMD8028 support") Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Message-ID: <20240425185603.3295450-1-quic_amelende@quicinc.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: mediatek: mt7622: add "antsel" functionRafał Miłecki2024-05-031-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | MT7622 pinctrl has ANTSEL* pins. Linux support for those was added in the commit 19f599e83ac5 ("pinctrl: mediatek: mt7622: add antsel pins/groups"). Include them in binding. Cc: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Rob Herring <robh@kernel.org> Message-ID: <20240423045502.7778-2-zajec5@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: mediatek: mt7622: fix array propertiesRafał Miłecki2024-05-031-43/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | Some properties (function groups & pins) are meant to be arrays and should allow multiple entries out of enum sets. Use "items" for those. Mistake was noticed during validation of in-kernel DTS files. Fixes: b9ffc18c6388 ("dt-bindings: mediatek: convert pinctrl to yaml") Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Rob Herring <robh@kernel.org> Message-ID: <20240423045502.7778-1-zajec5@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'renesas-pinctrl-for-v6.10-tag1' of ↵Linus Walleij2024-04-291-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.10 - Add external interrupt pin groups on R-Car V4M, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and ↵Lad Prabhakar2024-03-261-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'output-enable' properties On the RZ/G3S SMARC platform, the 'input' property is utilized in gpio-hog nodes, and the 'output-enable' property is used for ETH0/1 TXC pins. Update the binding documentation to include these properties, addressing the following dtbs_check warnings: arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: pinctrl@11030000: key-1-gpio-hog: 'anyOf' conditional failed, one must be fixed: 'input' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: pinctrl@11030000: eth0: 'anyOf' conditional failed, one must be fixed: 'output-enable' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240313083828.5048-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | dt-bindings: pinctrl: qcom,pmic-mpp: add support for PM8901Herman van Hazendonk2024-04-171-0/+1
| | | | | | | | | | | | | | | | | | | | The PM8901 is used alongside the APQ8060/MSM8660 on the APQ8060 Dragonboard and HP TouchPad. It works the same as all others, so just add the compatible string for this variant. Signed-off-by: Herman van Hazendonk <github.com@herrie.org> Message-ID: <20240417073532.3718510-1-github.com@herrie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: qcom,pmic-gpio: Allow gpio-hog nodesLuca Weiss2024-04-121-0/+12
| | | | | | | | | | | | | | | | | | | | Allow specifying a GPIO hog, as already used on qcom-msm8974-lge-nexus5-hammerhead.dts. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Message-ID: <20240409-qcom-pmic-gpio-hog-v2-1-5ff812d2baed@z3ntu.xyz> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: mediatek: mt7622: add "gpio-ranges" propertyRafał Miłecki2024-04-121-0/+3
| | | | | | | | | | | | | | | | | | | | Allow specifying pin to GPIO mapping. It can be find in in-Linux DTS file for MT7622. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Message-ID: <20240408105128.30586-1-zajec5@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIH0108 and PMD8028 supportAnjelique Melendez2024-03-281-0/+20
| | | | | | | | | | | | | | | | | | | | Update the Qualcomm Technologies, Inc. PMIC GPIO binding documentation to include compatible strings for PMIH0108 and PMD8028 PMICs. Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Message-ID: <20240326220628.2392802-3-quic_amelende@quicinc.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: qcom,pmic-gpio: Add PMXR2230 and PM6450 supportDavid Collins2024-03-281-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Update the Qualcomm Technologies, Inc. PMIC GPIO binding documentation to include compatible strings for PMXR2230 and PM6450 PMICs. Signed-off-by: David Collins <quic_collinsd@quicinc.com> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com> Acked-by: Krzystof Kozlowski <krzystof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Message-ID: <20240326220628.2392802-2-quic_amelende@quicinc.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: qcom: update functions to match with driverTengfei Fan2024-03-281-34/+18
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some functions were consolidated in the SM4450 pinctrl driver, but they had not been updated in the binding file before the previous SM4450 pinctrl patch series was merged. Update functions in this binding file to match with SM4450 pinctrl driver. Some functions need to be consolidated and some functions need to be removed. The following functions are removed: - atest_char0, atest_char1, atest_char2, atest_char3 - atest_usb00, atest_usb01, atest_usb02, atest_usb03 - audio_ref - cci_async - cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4 - cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3 - coex_uart1 - cri_trng0, cri_trng1 - dbg_out - ddr_pxi0, ddr_pxi1 - dp0_hot - gcc_gp1, gcc_gp2, gcc_gp3 - ibi_i3c - jitter_bist - mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3 - mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, mi2s_mclk1 - nav_gpio0, nav_gpio1, nav_gpio2 - phase_flag0, phase_flag1, phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15, phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20, phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26, phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31, phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9 - pll_bist, pll_clk - prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3 - qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9 - qlink0_wmss - qup0_se5, qup0_se6, qup0_se7, qup1_se5, qup1_se6 - sd_write - tb_trig - tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3 - tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3 - tsense_pwm1, tsense_pwm2 - uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset - usb0_hs, usb0_phy - vsense_trigger The following functions are added: - atest_char - atest_usb0 - audio_ref_clk - cci - cci_async_in0 - cmu_rng - coex_uart1_rx, coex_uart1_tx - dbg_out_clk - ddr_pxi0_test, ddr_pxi1_test - gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk - ibi_i3c_qup0, ibi_i3c_qup1 - jitter_bist_ref - mdp_vsync - nav - phase_flag - pll_bist_sync, pll_clk_aux - prng_rosc - qlink0_wmss_reset - sd_write_protect - tb_trig_sdc1, tb_trig_sdc2 - tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout, tgu_ch3_trigout - tmess_prng - tsense_pwm1_out, tsense_pwm2_out - uim0, uim1 - usb0_hs_ac, usb0_phy_ps - vsense_trigger_mirnat - wlan1_adc_dtest0, wlan1_adc_dtest1 Fixes: 7bf8b78f86db ("dt-bindings: pinctrl: qcom: Add SM4450 pinctrl") Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Message-ID: <20240312025807.26075-3-quic_tengfan@quicinc.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'devicetree-for-6.9' of ↵Linus Torvalds2024-03-152-37/+116
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DT core: - Add cleanup.h based auto release of struct device_node pointers via __free marking and new for_each_child_of_node_scoped() iterator to use it. - Always create a base skeleton DT when CONFIG_OF is enabled. This supports several usecases of adding DT data on non-DT booted systems. - Move around some /reserved-memory code in preparation for further improvements - Add a stub for_each_property_of_node() for !OF - Adjust the printk levels on some messages - Fix __be32 sparse warning - Drop RESERVEDMEM_OF_DECLARE usage from Freescale qbman driver (currently orphaned) - Add Saravana Kannan and drop Frank Rowand as DT maintainers DT bindings: - Convert Mediatek timer, Mediatek sysirq, fsl,imx6ul-tsc, fsl,imx6ul-pinctrl, Atmel AIC, Atmel HLCDC, FPGA region, and xlnx,sd-fec to DT schemas - Add existing, but undocumented fsl,imx-anatop binding - Add bunch of undocumented vendor prefixes used in compatible strings - Drop obsolete brcm,bcm2835-pm-wdt binding - Drop obsolete i2c.txt which as been replaced with schema in dtschema - Add DPS310 device and sort trivial-devices.yaml - Enable undocumented compatible checks on DT binding examples - More QCom maintainer fixes/updates - Updates to writing-schema.rst and DT submitting-patches.rst to cover some frequent review comments - Clean-up SPDX tags to use 'OR' rather than 'or'" * tag 'devicetree-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (56 commits) dt-bindings: soc: imx: fsl,imx-anatop: add imx6q regulators of: unittest: Use for_each_child_of_node_scoped() of: Introduce for_each_*_child_of_node_scoped() to automate of_node_put() handling of: Add cleanup.h based auto release via __free(device_node) markings of: Move all FDT reserved-memory handling into of_reserved_mem.c of: Add KUnit test to confirm DTB is loaded of: unittest: treat missing of_root as error instead of fixing up x86/of: Unconditionally call unflatten_and_copy_device_tree() um: Unconditionally call unflatten_device_tree() of: Create of_root if no dtb provided by firmware of: Always unflatten in unflatten_and_copy_device_tree() dt-bindings: timer: mediatek: Convert to json-schema dt-bindings: interrupt-controller: fsl,intmux: Include power-domains support soc: fsl: qbman: Remove RESERVEDMEM_OF_DECLARE usage dt-bindings: fsl-imx-sdma: fix HDMI audio index dt-bindings: soc: imx: fsl,imx-iomuxc-gpr: add imx6 dt-bindings: soc: imx: fsl,imx-anatop: add binding dt-bindings: input: touchscreen: fsl,imx6ul-tsc convert to YAML dt-bindings: pinctrl: fsl,imx6ul-pinctrl: convert to YAML of: make for_each_property_of_node() available to to !OF ...
| * dt-bindings: pinctrl: fsl,imx6ul-pinctrl: convert to YAMLSebastian Reichel2024-03-052-37/+116
| | | | | | | | | | | | | | | | | | | | Convert i.MX6UL pinctrl bindings to YAML. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sebastian Reichel <sre@kernel.org> Link: https://lore.kernel.org/r/20240226212740.2019837-2-sre@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
* | dt-bindings: pinctrl: qcom: update compatible name for match with driverTengfei Fan2024-03-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use compatible name "qcom,sm4450-tlmm" instead of "qcom,sm4450-pinctrl" to match the compatible name in sm4450 pinctrl driver. Fixes: 7bf8b78f86db ("dt-bindings: pinctrl: qcom: Add SM4450 pinctrl") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240129092512.23602-2-quic_tengfan@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: Add bindings for Awinic AW9523/AW9523BAngeloGioacchino Del Regno2024-03-051-0/+139
| | | | | | | | | | | | | | | | | | | | | | Add bindings for the Awinic AW9523/AW9523B I2C GPIO Expander driver. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: David Bauer <mail@david-bauer.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210624214458.68716-1-mail@david-bauer.net [Fixed up minor bugs found by new checking tools] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: at91: add sam9x7Varshini Rajendran2024-02-291-0/+2
| | | | | | | | | | | | | | | | | | Add device tree binding for SAM9X7 pin controller. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240223172531.671993-1-varshini.rajendran@microchip.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: mobileye,eyeq5-pinctrl: add bindingsThéo Lebrun2024-02-291-0/+242
| | | | | | | | | | | | | | | | | | | | Add dt-schema type bindings for the Mobileye EyeQ5 pin controller. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20240227-mbly-clk-v8-1-c57fbda7664a@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'renesas-pinctrl-for-v6.9-tag2' of ↵Linus Walleij2024-02-261-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.9 (take two) - Add support for the R-Car V4M (R8A779H0) SoC, - Add support for suspend/resume on the RZ/G2L family, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | dt-bindings: pinctrl: renesas,pfc: Document R-Car V4M supportGeert Uytterhoeven2024-02-201-0/+1
| |/ | | | | | | | | | | | | | | | | Document support for the Pin Function Controller (PFC) in the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/56685dc04af3cee7cb3751e855ed5b3679b14122.1706264667.git.geert+renesas@glider.be
* | dt-bindings: pinctrl: cy8c95x0: Update gpio-reserved-rangesNaresh Solanki2024-02-091-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | Update maxItems to 60 for gpio-reserved-ranges to allow multiple gpio reserved ranges. Add input-enable property to allow configuring a pin as input. Also update example. Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240206112501.715042-1-naresh.solanki@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: nvidia,tegra234-pinmux: Restructure common schemaRob Herring2024-02-093-53/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The structure of the NVIDIA Tegra234 common pinmux schema doesn't work for restricting properties because a child node schema can't be extended with additional properties from another schema defining the same child node. The 2 child node schemas are evaluated independently as the schemas are not recursively combined in any way. As the common schema is almost all the child node schema anyways, just remove the parent node from the common schema. Then add 'reg' and adjust the $ref's in the users of the common schema. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240202223454.1667383-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctr: pinctrl-zynq: Fix compatible stringMichal Simek2024-01-311-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compatible string doesn't really match with compatible string listed in the driver itself. While binding was converted from txt to yaml xlnx,zynq-pinctrl was listed as compatible string but example was using xlnx,pinctrl-zynq and also this string is used in all DTSes. xlnx,zynq-pinctrl is used only in dt binding and not present in any DT which is stable for quite a long time that's why use old compatible string and update binding document instead of starting to use unused compatible string. Fixes: 153df45acda0 ("dt-bindings: pinctrl: pinctrl-zynq: Convert to yaml") Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/c1307a4dd5e30290acacc786cb2170deb9eaa539.1706087258.git.michal.simek@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: nuvoton,npcm845: Drop redundant type for "slew-rate"Rob Herring2024-01-311-1/+0
| | | | | | | | | | | | | | | | | | | | pincfg-node.yaml already defines the type for "slew-rate", so drop the type from the nuvoton,npcm845-pinctrl binding. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240124190106.1540585-2-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: Unify "input-debounce" schemaRob Herring2024-01-314-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | nuvoton,npcm845-pinctrl defines the common "input-debounce" property as an array rather than an scalar. Update the common definition to expand it to an uint32-array, and update all the users of the property with array constraints. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240124190106.1540585-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | dt-bindings: pinctrl: amlogic: narrow regex for unit address to hex numbersKrzysztof Kozlowski2024-01-285-5/+5
|/ | | | | | | | | | Regular expression used to match the unit address part should not allow non-hex numbers. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240123083511.21063-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v6.8-1' of ↵Linus Torvalds2024-01-1761-772/+834
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "For this kernel cycle I managed an immutable branch for the PEF2256 WAN framer that has some pin control portions. It already landed in your tree through the net pull request but here it is mentioned again. The most interesting is perhaps the Samsung Exynos subdrivers for the Tensor SoC used in Google Pixel 6 and the ExynosAuto subdriver for automotive. Along with the earlier merged Tesla FSD subdriver it shows some of the versatile uses of the Samsung Exynos silicon. It is also used in the latest version of Axis Communications ARTPEC chips so it is a very widely deployed SoC family. We also have the Intel Meteor Lake SoC which I think is for laptops. It's a pretty interesting chip with Xe graphics and integrated PCH. Core changes: - A new PINCTRL_GROUP_DESC() infrastructure macro is added and used in different drivers, generic group description struct group_desc is now used all over the place. New drivers: - New driver for the Texas Instruments TPS6494 Power Management IC. - New driver for the Lantic PEF2256 framer pin multiplexer. This IC has some pins that can be reconfigured in different ways. The actual driver comes on an immutable branch with the net WAN parts, the IC is some latest-and-greatest serial line funnel for e.g. wireless access points. - New subdriver for the Samsung Exynos Auto V920 pin controller, used for automotive applications. - New subdriver for the Samsung "GS101" SoC pin controller, this is the Google "Tensor" SoC used in the Google Pixel 6. - New subdriver for the Intel Meteor Point SoC pin controller. - New subdriver for the Qualcomm SM8650 top level (TLMM) and LPASS pin controllers. - New subdriver for the Qualcomm X1E80100 top level (TLMM) pin controller. - New subdriver for the Qualcomm SM4450 top level (TLMM) pin controller. - The "single" pin controller now supports the Texas Instruments J7200 SoC. Improvements: - Intel has created a new (Intel-)generic pin controller driver that is now used by all contemporary Intel platforms. - Intel is now also making use of some cleanup helpers. - Enble 910 Ohm bias in the Intel Tangier driver. - The Samsung driver now suppors irq_set_affinity() in it's IRQ chip giving support for non wake up external gpio interrupts" * tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits) pinctrl: samsung: constify iomem pointers pinctrl: cy8c95x0: Cache muxed registers dt-bindings: pinctrl: xilinx: Rename *gpio to *gpio-grp pinctrl: qcom: lpass-lpi: remove duplicated include dt-bindings: pinctrl: qcom: drop common properties and allow wakeup-parent dt-bindings: pinctrl: qcom: drop common properties dt-bindings: pinctrl: qcom,ipq5018-tlmm: use common TLMM bindings dt-bindings: pinctrl: qcom,x1e80100-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sm8650-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sm8550-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sdx75-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sa8775p-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,qdu1000-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom: create common LPASS LPI schema pinctrl: qcom: sm4450: dd SM4450 pinctrl driver dt-bindings: pinctrl: qcom: Add SM4450 pinctrl dt-bindings: pinctrl: qcom,pmic-mpp: clean up example pinctrl: intel: Add Intel Meteor Point pin controller and GPIO support pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins pinctrl: renesas: rzg2l: Add output enable support ...
| * dt-bindings: pinctrl: xilinx: Rename *gpio to *gpio-grpMichal Simek2023-12-202-2/+2
| | | | | | | | | | | | | | | | | | | | | | Anything ending with gpio/gpios is taken as gpio phande/description which is reported as the issue coming from gpio-consumer.yaml schema. That's why rename the gpio suffix to gpio-grp to avoid name collision. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/2e3a1f1f57cf929bd05115bc081e6d01d5a53443.1702996859.git.michal.simek@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: qcom: drop common properties and allow wakeup-parentKrzysztof Kozlowski2023-12-206-46/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop common properties already defined in referenced common Qualcomm SoC TLMM bindings and use "unevaluatedProperties: false". This makes the binding smaller and easier to review. Additionally this allows now "wakeup-parent" property coming from common TLMM bindings. In few places move the "required:" block to bottom, to match convention. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231208215534.195854-10-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: qcom: drop common propertiesKrzysztof Kozlowski2023-12-2037-376/+95
| | | | | | | | | | | | | | | | | | | | | | | | Drop common properties already defined in referenced common Qualcomm SoC TLMM bindings and use "unevaluatedProperties: false". This makes the binding smaller and easier to review. In few places move the "required:" block to bottom, to match convention. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231208215534.195854-9-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: qcom,ipq5018-tlmm: use common TLMM bindingsKrzysztof Kozlowski2023-12-201-8/+4
| | | | | | | | | | | | | | | | | | | | Reference common Qualcomm SoC TLMM bindings to drop commonly used properties and also bring other schemas for common definitions. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231208215534.195854-8-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * dt-bindings: pinctrl: qcom,x1e80100-tlmm: restrict number of interruptsKrzysztof Kozlowski2023-12-201-1/+3
| | | | | | | | | | | | | | | | | | | | X1E80100 TLMM pin controller comes with only one interrupt, so narrow the number of interrupts previously defined in common TLMM bindings. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231208215534.195854-7-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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