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* dt-bindings: sifive-l2-cache: Fix 'select' matchingRob Herring2021-08-191-4/+4
* dt-bindings: Drop redundant minItems/maxItemsRob Herring2021-06-211-1/+0
* dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoCAtish Patra2021-04-261-0/+27
* Merge tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-02-264-9/+97
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| * dt-bindings: update risc-v cpu propertiesDamien Le Moal2021-02-221-0/+2
| * dt-bindings: add Canaan boards compatible stringsDamien Le Moal2021-02-221-0/+47
| * dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched boardYash Shah2021-01-071-5/+12
| * dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoCYash Shah2021-01-071-0/+6
| * dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFiv...Yash Shah2021-01-071-4/+30
* | dt-bindings: Add missing array size constraintsRob Herring2021-01-111-0/+1
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* dt-bindings: Explicitly allow additional properties in board/SoC schemasRob Herring2020-10-261-0/+3
* dt-bindings: More whitespace clean-ups in schema filesRob Herring2020-10-261-2/+2
* dt-bindings: Explicitly allow additional properties in common schemasRob Herring2020-10-071-0/+2
* dt-bindings: riscv: sifive-l2-cache: convert bindings to json-schemaSagar Kadam2020-10-012-51/+98
* dt-bindings: Remove cases of 'allOf' containing a '$ref'Rob Herring2020-05-031-11/+9
* dt-bindings: riscv: Fix CPU schema errorsRob Herring2019-10-231-16/+13
* dt-bindings: riscv: fix the schema compatible string for the HiFive Unleashed...Paul Walmsley2019-08-081-1/+1
* dt-bindings: riscv: remove obsolete cpus.txtPaul Walmsley2019-08-082-162/+12
* dt-bindings: Update the riscv,isa string descriptionAtish Patra2019-08-081-0/+4
* dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodesRob Herring2019-07-201-82/+61
* dt-bindings: riscv: resolve 'make dt_binding_check' warningsPaul Walmsley2019-06-261-12/+14
* dt-bindings: riscv: convert cpu binding to json-schemaPaul Walmsley2019-06-171-0/+168
* dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540Paul Walmsley2019-06-171-0/+25
* RISC-V: Add DT documentation for SiFive L2 Cache ControllerYash Shah2019-05-161-0/+51
* dt-bindings: RISC-V CPU BindingsPalmer Dabbelt2017-09-251-0/+162
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