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* arm64: dts: amlogic: axg: fix tdm audio-controller clock orderNeil Armstrong2024-06-071-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following: audio-controller-0: clock-names:0: 'sclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-0: clock-names:1: 'lrclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-0: clock-names:2: 'mclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-1: clock-names:0: 'sclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-1: clock-names:1: 'lrclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-1: clock-names:2: 'mclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-2: clock-names:0: 'sclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-2: clock-names:1: 'lrclk' was expected from schema $id: http://devicetree.org/schemas/sound/amlogic,axg-tdm-iface.yaml# audio-controller-2: clock-names:2: 'mclk' was expected Tested-by: Christian Hewitt <christianshewitt@gmail.com> Link: https://lore.kernel.org/r/20240606-topic-amlogic-upstream-bindings-fixes-dts-v1-8-62e812729541@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: amlogic: axg: initialize default SoC capacitanceDmitry Rokosov2024-02-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The capacitance value is required for the usage of the cpufreq cooling device and power_allocator thermal governor in the appropriate energy model. It helps to compute the power estimated by the SoC at the appropriate frequency. If it is the frequency of an existing OPP, or at the frequency of the first OPP above the requested value otherwise. The power is estimated as P = C * V^2 * f, with C being the SoC's capacitance and V and f respectively representing the voltage and frequency of the OPP. Since AXG SoC doesn't have SCMI protocol support, we need to initialize capacitance using the 'dynamic-power-coefficient' DT entry. Its value is retrieved from the vendor kernel, and it gives us the following freq2power mapping: +-----------+--------+ | frequency,| power, | | MHz | uW | +-----------+--------+ | 100 | 10354 | +-----------+--------+ | 250 | 27104 | +-----------+--------+ | 500 | 55447 | +-----------+--------+ | 667 | 77327 | +-----------+--------+ | 1000 | 129024 | +-----------+--------+ | 1200 | 164656 | +-----------+--------+ | 1296 | 192489 | +-----------+--------+ | 1416 | 239870 | +-----------+--------+ Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240209212816.11187-3-ddrokosov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: amlogic: axg: move cpu cooling-cells to common dtsiDmitry Rokosov2024-02-131-0/+4
| | | | | | | | | | | The CPU cooling-cells property should be located in the meson-axg common dtsi, as it is required for all AXG-based boards with DVFS. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Viacheslav Bocharov <adeep@lexina.in> Link: https://lore.kernel.org/r/20240209212816.11187-2-ddrokosov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: amlogic: meson-axg: pinctrl node for NANDArseniy Krasnov2023-11-271-0/+23
| | | | | | | | | Add pinctrl node for the Meson NAND controller. Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231109094504.131265-1-avkrasnov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: amlogic: meson-axg: Meson NAND nodeArseniy Krasnov2023-09-111-0/+13
| | | | | | | | | Add description of the Meson NAND controller node. Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230828133647.3712644-1-avkrasnov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: amlogic: add missing cache propertiesKrzysztof Kozlowski2023-05-091-0/+1
| | | | | | | | | | | | As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: meson-a1-ad401.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230421223211.115612-1-krzysztof.kozlowski@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* Merge tag 'soc-dt-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2023-02-201-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull SoC DT updates from Arnd Bergmann: "About a quarter of the changes are for 32-bit arm, mostly filling in device support for existing machines and adding minor cleanups, mostly for Qualcomm and Samsung based machines. Two new 32-bit SoCs are added, both are quad-core Cortex-A7 chips from Rockchips that have been around for a while but were lacking kernel support so far: RV1126 is a Vision SoC with an NPU and is used in the Edgeble Neural Compute Module 2(Neu2) board, while RK3128 is design for TV boxes and so far only comes with a dts for its refernece design. The other 32-bit boards that were added are two ASpeed AST2600 based BMC boards, the Microchip sam9x60_curiosity development board (Armv5 based!), the Enclustra PE1 FPGA-SoM baseboard, and a few more boards for i.MX53 and i.MX6ULL. On the RISC-V side, there are fewer patches, but a total of ten new single-board computers based on variations of the Allwinner D1/T113 chip, plus one more board based on Microchip Polarfire. As usual, arm64 has by far the most changes here, with over 700 non-merge changesets, among them over 400 alone for Qualcomm. The newly added SoCs this time are all recent high-end embedded SoCs for various markets, each on comes with support for its reference board: - Qualcomm SM8550 (Snapdragon 8 Gen 2) for mobile phones - Qualcomm QDU1000/QRU1000 5G RAN platform - Rockchips RK3588/RK3588s for tablets, chromebooks and SBCs - TI J784S4 for industrial and automotive applications In total, there are 46 new arm64 machines: - Reference platforms for each of the five new SoCs - Three Amlogic based development boards - Six embedded machines based on NXP i.MX8MM and i.MX8MP - The Mediatek mt7986a based Banana Pi R3 router - Six tablets based on Qualcomm MSM8916 (Snapdragon 410), SM6115 (Snapdragon 662) and SM8250 (Snapdragon 865) - Two LTE dongles, also based on MSM8916 - Seven mobile phones, based on Qualcomm MSM8953 (Snapdragon 610), SDM450 and SDM632 - Three chromebooks based on Qualcomm SC7280 (Snapdragon 7c) - Nine development boards based on Rockchips RK3588, RK3568, RK3566 and RK3328. - Five development machines based on TI K3 (AM642/AM654/AM68/AM69) The cleanup of dtc warnings continues across all platforms, adding to the total number of changes" * tag 'soc-dt-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (1035 commits) dt-bindings: riscv: correct starfive visionfive 2 compatibles ARM: dts: socfpga: Add enclustra PE1 devicetree dt-bindings: altera: Add enclustra mercury PE1 arm64: dts: qcom: msm8996: align RPM G-Link clock-controller node with bindings arm64: dts: qcom: qcs404: align RPM G-Link node with bindings arm64: dts: qcom: ipq6018: align RPM G-Link node with bindings arm64: dts: qcom: sm8550: remove invalid interconnect property from cryptobam arm64: dts: qcom: sc7280: Adjust zombie PWM frequency arm64: dts: qcom: sc8280xp-pmics: Specify interrupt parent explicitly arm64: dts: qcom: sm7225-fairphone-fp4: enable remaining i2c busses arm64: dts: qcom: sm7225-fairphone-fp4: move status property down arm64: dts: qcom: pmk8350: Use the correct PON compatible arm64: dts: qcom: sc8280xp-x13s: Enable external display arm64: dts: qcom: sc8280xp-crd: Introduce pmic_glink arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks arm64: dts: qcom: sm8350-hdk: enable GPU arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes arm64: dts: qcom: sm8350: finish reordering nodes arm64: dts: qcom: sm8350: move more nodes to correct place arm64: dts: qcom: sm8350: reorder device nodes ...
| * arm64: dts: amlogic: meson-gx: add missing SCPI sensors compatibleNeil Armstrong2023-01-261-1/+1
| | | | | | | | | | | | | | | | | | | | Fixes: scpi: sensors:compatible: 'oneOf' conditional failed, one must be fixed: ['amlogic,meson-gxbb-scpi-sensors'] is too short 'arm,scpi-sensors' was expected Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-3-44351528957e@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
| * arm64: dts: amlogic: meson-axg: fix SCPI clock dvfs node nameNeil Armstrong2023-01-261-1/+1
| | | | | | | | | | | | | | | | Fixes: scpi: clocks: 'clock-controller' does not match any of the regexes: '^clocks-[0-9a-f]+$', 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-2-44351528957e@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
| * arm64: dts: amlogic: Fix non-compliant SD/SDIO node namesHeiner Kallweit2023-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | mmc-controller.yaml defines "^mmc(@.*)?$" as node name pattern. In preparation of adding schema-based validation fix the node name in two affected files. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/55c53e8d-6b30-51bf-edf6-b5b67887bd0a@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* | arm64: dts: meson-axg: Make mmc host controller interrupts level-sensitiveHeiner Kallweit2023-02-101-2/+2
|/ | | | | | | | | | | | | | | | | | | | The usage of edge-triggered interrupts lead to lost interrupts under load, see [0]. This was confirmed to be fixed by using level-triggered interrupts. The report was about SDIO. However, as the host controller is the same for SD and MMC, apply the change to all mmc controller instances. [0] https://www.spinics.net/lists/linux-mmc/msg73991.html Fixes: 221cf34bac54 ("ARM64: dts: meson-axg: enable the eMMC controller") Reported-by: Peter Suti <peter.suti@streamunlimited.com> Tested-by: Vyacheslav Bocharov <adeep@lexina.in> Tested-by: Peter Suti <peter.suti@streamunlimited.com> Cc: stable@vger.kernel.org Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/c00655d3-02f8-6f5f-4239-ca2412420cad@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: Update cache properties for amlogicPierre Gondois2022-11-071-0/+1
| | | | | | | | | | | | | | | The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20221107155825.1644604-4-pierre.gondois@arm.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: amlogic: adjust whitespace around '='Krzysztof Kozlowski2022-06-101-1/+1
| | | | | | | | | | | Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220526204552.832961-1-krzysztof.kozlowski@linaro.org
* arm64: dts: meson: set 128bytes FIFO size on uart ANeil Armstrong2021-06-011-0/+1
| | | | | | | | | The first UART controller in "Everything-Else" power domain, usually used for Bluetooth HCI has 128bytes FIFO depth. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210518075833.3736038-4-narmstrong@baylibre.com
* arm64: dts: amlogic: misc DT schema fixupsKevin Hilman2021-04-221-1/+0
| | | | | | | | | | Take a pass at cleaning up a bunch of warnings from 'make dtbs_check' that have crept in. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210421204833.18523-1-khilman@baylibre.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Revert "arm64: dts: amlogic: add missing ethernet reset ID"Neil Armstrong2021-01-261-2/+0
| | | | | | | | | | | | | | | | | It has been reported on IRC and in KernelCI boot tests, this change breaks internal PHY support on the Amlogic G12A/SM1 Based boards. We suspect the added signal to reset more than the Ethernet MAC but also the MDIO/(RG)MII mux used to redirect the MAC signals to the internal PHY. This reverts commit f3362f0c18174a1f334a419ab7d567a36bd1b3f3 while we find and acceptable solution to cleanly reset the Ethernet MAC. Reported-by: Corentin Labbe <clabbe@baylibre.com> Acked-by: Jérôme Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20210126080951.2383740-1-narmstrong@baylibre.com
* arm64: dts: meson-axg: add GE2D nodeNeil Armstrong2020-12-071-0/+9
| | | | | | | | This adds the node for the GE2D accelerator unit. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201202174417.3778306-5-narmstrong@baylibre.com
* arm64: dts: meson-axg: add PCIe nodesNeil Armstrong2020-11-301-0/+61
| | | | | | | | | | This adds the nodes for the : - AXG PCIe PHY, using the shared analog PCIe/MIPI DSI PHY - 2x AXG PCIe controllers Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120153229.3920123-4-narmstrong@baylibre.com
* arm64: dts: meson-axg: add MIPI DSI PHY nodesNeil Armstrong2020-11-301-0/+19
| | | | | | | | | | This adds the nodes for : - MIPI DSI+PCIe analog phy - MIPI D-PHY Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120152131.3918814-3-narmstrong@baylibre.com
* arm64: dts: meson-axg: add PWRC nodeNeil Armstrong2020-11-301-0/+42
| | | | | | | | This adds the power controller PWRC node and the corresponding ethernet power domain. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120152131.3918814-2-narmstrong@baylibre.com
* arm64: dts: amlogic: add missing ethernet reset IDAnand Moon2020-10-201-0/+2
| | | | | | | | | | | Add reset external reset of the ethernet mac controller Signed-off-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201020120141.298240-1-jbrunet@baylibre.com
* arm64: dts: meson-axg: add USB nodesNeil Armstrong2020-10-051-0/+50
| | | | | | | | | | This adds the USB Glue node, with the USB2 & USB3 controllers along the single USB2 PHY node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clockMartin Blumenstingl2020-07-131-2/+4
| | | | | | | | | | | Add the "timing-adjustment" clock now that we know how it is connected to the PRG_ETHERNET registers. It is used internally to generate the RGMII RX delay on the MAC side (if needed). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200620162347.26159-1-martin.blumenstingl@googlemail.com
* arm64: dts: meson: fixup SCP sram nodesNeil Armstrong2020-04-291-3/+3
| | | | | | | | | | | | | | The GX and AXG SCP sram nodes were using invalid compatible and node names for the sram entries. Fixup the sram entries node names, and use proper compatible for them. It notably fixes: sram@c8000000: 'scp-shmem@0', 'scp-shmem@200' do not match any of the regexes: '^([a-z]*-)?sram(-section)?@[a-f0-9]+$', 'pinctrl-[0-9]+' Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200326165958.19274-3-narmstrong@baylibre.com
* arm64: dts: meson: add audio fifo depthsJerome Brunet2020-01-081-0/+6
| | | | | | | | Add the property describing the depth of the audio fifo on the axg, g12a and sm1 SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: Link nvmem and secure-monitor nodesCarlo Caione2019-10-031-0/+1
| | | | | | | The former is going to use the latter to retrieve the efuses data. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: axg: fix audio fifo reg sizeJerome Brunet2019-10-031-6/+6
| | | | | | | | | The register region size initially is too small to access all the fifo registers. Fixes: f2b8f6a93357 ("arm64: dts: meson-axg: add audio fifos") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-axg: fix MHU compatibleNeil Armstrong2019-08-291-1/+1
| | | | | | | | This fixes the following DT schemas check errors: meson-axg-s400.dt.yaml: mailbox@ff63c404: compatible:0: 'amlogic,meson-gx-mhu' is not one of ['amlogic,meson-gxbb-mhu'] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: fix ethernet mac reg formatNeil Armstrong2019-08-291-2/+2
| | | | | | | | | | | | | | | | | This fixes the following DT schemas check errors: meson-axg-s400.dt.yaml: soc: ethernet@ff3f0000:reg:0: [0, 4282318848, 0, 65536, 0, 4284695872, 0, 8] is too long meson-axg-s400.dt.yaml: ethernet@ff3f0000: reg: [[0, 4282318848, 0, 65536, 0, 4284695872, 0, 8]] is too short meson-g12a-u200.dt.yaml: soc: ethernet@ff3f0000:reg:0: [0, 4282318848, 0, 65536, 0, 4284695872, 0, 8] is too long meson-g12a-u200.dt.yaml: ethernet@ff3f0000: reg: [[0, 4282318848, 0, 65536, 0, 4284695872, 0, 8]] is too short meson-gxbb-nanopi-k2.dt.yaml: soc: ethernet@c9410000:reg:0: [0, 3376480256, 0, 65536, 0, 3364046144, 0, 4] is too long meson-gxl-s805x-libretech-ac.dt.yaml: soc: ethernet@c9410000:reg:0: [0, 3376480256, 0, 65536, 0, 3364046144, 0, 4] is too lon while here, also drop the redundant reg property from meson-gxl.dtsi because it had the same value as meson-gx.dtsi from which it inherits. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: add ethernet fifo sizesJerome Brunet2019-08-091-0/+2
| | | | | | | | | | | | | | If unspecified in DT, the fifo sizes are not automatically detected by the dwmac1000 dma driver and the reported fifo sizes default to 0. Because of this, flow control will be turned off on the device. Add the fifo sizes provided by the datasheets in the SoC in DT so flow control may be enabled if necessary. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: add dwmac-3.70a to ethmac compatible listJerome Brunet2019-06-111-1/+3
| | | | | | | | | After discussing with Amlogic, the Synopsys GMAC version used by the gx and axg family is the 3.70a. Set this is in DT Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: fix mmc pin biasJerome Brunet2019-05-211-7/+24
| | | | | | | | Clk pin does not require bias, data strobe should be pulled low. The rest of the pin (data and cmd) are pulled up. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* Merge tag 'amlogic-dt64' of ↵Arnd Bergmann2019-02-151-0/+25
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.1 - new board: G12a-based x96 max - G12a: add peripheral clock controller and clock measure support - s400: fix SD/eMMC max rate issues - s400: audio: add sp/dif in support - GX: support simplefb * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson: add g12a x96 max board dt-bindings: arm: amlogic: add amediatech x96-max bindings arm64: dts: meson: g12a: add peripheral clock controller arm64: dts: meson: g12a: add clk measure support arm64: dts: meson: axg: add clk measure support arm64: dts: meson: fix g12a buses arm64: dts: meson-axg: add efuse device arm64: dts: meson: s400: fix emmc maximum rate arm64: dts: meson: s400: enable sdr104 on sdio arm64: dts: meson-gx: add support for simplefb dt-bindings: meson: add specific simplefb bindings arm64: dts: meson-gx: Add canvas provider node to the vpu arm64: dts: meson-axg: s400: add spdifin to the sound card arm64: dts: meson-axg: s400: add spdif-dir codec arm64: dts: meson-axg: add spdifin Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * arm64: dts: meson: axg: add clk measure supportJerome Brunet2019-02-071-0/+5
| | | | | | | | | | | | | | | | Add the clock measure device to the axg SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * arm64: dts: meson-axg: add efuse deviceJerome Brunet2019-01-171-0/+8
| | | | | | | | | | | | | | Add efuse to the AXG family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| * arm64: dts: meson-axg: add spdifinJerome Brunet2019-01-101-0/+12
| | | | | | | | | | | | | | Add the SPDIF input device of the axg audio subsystem Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | arm64: dts: Remove inconsistent use of 'arm,armv8' compatible stringRob Herring2019-01-301-4/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: dts: meson: Fix IRQ trigger type for macirqCarlo Caione2018-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | A long running stress test on a custom board shipping an AXG SoCs and a Realtek RTL8211F PHY revealed that after a few hours the connection speed would drop drastically, from ~1000Mbps to ~3Mbps. At the same time the 'macirq' (eth0) IRQ would stop being triggered at all and as consequence the GMAC IRQs never ACKed. After a painful investigation the problem seemed to be due to a wrong defined IRQ type for the GMAC IRQ that should be LEVEL_HIGH instead of EDGE_RISING. The change in the macirq IRQ type also solved another long standing issue affecting this SoC/PHY where EEE was causing the network connection to die after stressing it with iperf3 (even though much sooner). It's now possible to remove the 'eee-broken-1000t' quirk as well. Fixes: feb3cbea0946 ("ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage") Fixes: 6d28d577510f ("ARM64: dts: meson-axg: fix ethernet stability issue") Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-axg: Enable GPIO interrupt controllerCarlo Caione2018-12-071-2/+2
| | | | | | | | | Enable the GPIO interrupt controller for the AXG SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: add clock controller clock inputsJerome Brunet2018-12-041-0/+4
| | | | | | | Add the clock inputs of the clock controllers Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-axg: remove alternate xtalJerome Brunet2018-12-041-7/+0
| | | | | | | | | | | | | There is actually no alternate xtal on any of the axg board I have seen so far. The 32k is actually generated internally, deriving from the 24MHz main xtal. Amlogic SoC also have the option to provide the 32k reference externally, through one of the AO pads, but no platform is using this ATM. Fixes: 5e395e146667 ("ARM64: dts: meson-axg: add an 32K alt aoclk") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-axg: Enable watchdog on Meson AXG SoCsCarlo Caione2018-12-041-0/+6
| | | | | | | | Add the watchdog node also on the AXG platforms. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: consistently disable pin biasJerome Brunet2018-11-291-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | On Amlogic chipsets, the bias set through pinconf applies to the pad itself, not only the GPIO function. This means that even when we change the function of the pad from GPIO to anything else, the bias previously set still applies. As we have seen with the eMMC, depending on the bias type and the function, it may trigger problems. The underlying issue is that we inherit whatever was left by previous user of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual setup we will get is undefined. There is nothing mentioned in the documentation about pad bias and pinmux function, however leaving it undefined is not an option. This change consistently disable the pad bias for every pinmux functions. It seems to work well, we can only assume that the necessary bias (if any) is already provided by the pin function itself. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: disable pad bias for mmc pinmuxesJerome Brunet2018-11-291-0/+2
| | | | | | | | | | | In some cases (such as a boot from SPI) the bootloader or the ROM code may leave a bias pull-down on the mmc pins. If so the MMC will fail during the initialisation. Explicitly disabling the pinmux solves the problem. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: remove extra subnode in mmc clk_gate pinmuxJerome Brunet2018-11-291-6/+0
| | | | | | | | | In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for the function definition, the other for the bias. This is not necessary since we can define the function and the bias in the same subnode. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-axg: enable SCPIJerome Brunet2018-11-291-0/+26
| | | | | | | | | Enable SCPI on the axg platform, with cpu clock and hwmon (core temperature) support Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-axg: correct sram shared mem unit-addressJerome Brunet2018-11-291-2/+2
| | | | | | | | Correct the unit-address in the node name of the SRAM shared memory Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-axg: fix mailbox addressJerome Brunet2018-11-291-2/+2
| | | | | | | | | | MHU mailbox address is wrong. Fixing it enables the mailboxes on the A113. These mailboxes are needed for SCPI Fixes: 9d59b708500f ("arm64: dts: meson-axg: add initial A113D SoC DT support") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-axg: add secure monitorJerome Brunet2018-11-291-0/+4
| | | | | | | | | Add the secure monitor device to the axg platform. With this, we can read the SoC serial number. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-axg: fix dtc warning about unit addressJerome Brunet2018-11-291-3/+3
| | | | | | | | | | | | | | section 2.2.1 of the DT specs says: " If the node has no reg property, the @unit-address must be omitted and the node-name alone differentiates the node from other nodes at the same level in the tree" Simply replace the '@' with a '-' to fix this warning. Cc: Fabio Estevam <festevam@gmail.com> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 05:43:41 +0000