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* arm64: dts: imx8mm-venice-gw7902(3): add #address-cells for gsc@20Frank Li2024-09-041-0/+2
| | | | | | | | | Add #address-cells and #size-cells for gsc@20 node to fix below warning: arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb: gsc@20: '#address-cells' is a required property Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: freescale: imx8m*-venice-*: fix gw,gsc dt-schema warningsTim Harvey2024-07-011-2/+0
| | | | | | | | Fix the dt-schema warnings due to #address-cells/#size-cells being unnecessary when there are no children with reg cells. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: imx8mm-venice-gw790: Pass GSC address/size-cellsFabio Estevam2023-10-101-0/+2
| | | | | | | | | | | | | | | | Per gateworks-gsc.yaml, #address-cells and #size-cells are mandatory properties. Pass them to fix the following schema warning: imx8mm-venice-gw7903.dtb: gsc@20: '#address-cells' is a required property from schema $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml# imx8mm-venice-gw7903.dtb: gsc@20: '#size-cells' is a required property from schema $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: imx8mm/p-venice: Remove lis2de12 interrupt-namesFabio Estevam2023-09-251-1/+0
| | | | | | | | | | | | | | According to st,st-sensors.yaml, the 'interrupt-names' property is not a valid one. Remove it to fix the following schema warnings: imx8mp-venice-gw73xx-2x.dtb: accelerometer@19: 'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/iio/st,st-sensors.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2023-08-301-15/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM devicetree updates from Arnd Bergmann: "These are the devicetree updates for Arm and RISC-V based SoCs, mainly from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips, Samsung, ST and Starfive. Only a few new SoC got added: - TI AM62P5, a variant of the existing Sitara AM62x family - Intel Agilex5, an FPGFA platform that includes an Cortex-A76/A55 SoC. - Qualcomm ipq5018 is used in wireless access points - Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile phone platform. In total, 29 machines get added, which is low because of the summer break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST, Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of these are development and reference boards. Despite not adding a lot of new machines, there are over 700 patches in total, most of which are cleanups and minor fixes" * tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (735 commits) arm64: dts: use capital "OR" for multiple licenses in SPDX ARM: dts: use capital "OR" for multiple licenses in SPDX arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved ARM: dts: qcom: apq8064: add support to gsbi4 uart riscv: dts: change TH1520 files to dual license riscv: dts: thead: add BeagleV Ahead board device tree dt-bindings: riscv: Add BeagleV Ahead board compatibles ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs ARM: dts: stm32: support display on stm32f746-disco board ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco ARM: dts: stm32: add pin map for LTDC on stm32f7 ARM: dts: stm32: add ltdc support on stm32f746 MCU arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sdm670: Add PDC riscv: dts: starfive: fix jh7110 qspi sort order ...
| * arm64: dts: imx: Pass a single BD71847 clock entryFabio Estevam2023-08-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | Pass a single BD71847 clock entry to fix the following schema warning: imx8mm-var-som-symphony.dtb: pmic@4b: clocks: [[22], [0]] is too long from schema $id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * arm64: dts: imx8mm-venice-gw7904: enable UART1 hardware flow controlTim Harvey2023-07-171-14/+4
| | | | | | | | | | | | | | | | | | On the GW7904 uart1 can use UART3_TX/RX for hardware flow control which was the desired default configuration. Remove uart3 and configure uart1 for hardware flow control. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | arm64: dts: imx8mm-venice-gw7904: disable disp_blk_ctrlTim Harvey2023-07-171-0/+4
|/ | | | | | | | | | | | | | The GW7904 does not connect the VDD_MIPI power rails thus MIPI is disabled. However we must also disable disp_blk_ctrl as it uses the pgc_mipi power domain and without it being disabled imx8m-blk-ctrl will fail to probe: imx8m-blk-ctrl 32e28000.blk-ctrl: error -ETIMEDOUT: failed to attach power domain "mipi-dsi" imx8m-blk-ctrl: probe of 32e28000.blk-ctrl failed with error -110 Fixes: b999bdaf0597 ("arm64: dts: imx: Add i.mx8mm Gateworks gw7904 dts support") Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: imx8mm: Deduplicate PCIe clock-names propertyMarek Vasut2023-01-261-3/+2
| | | | | | | | | | | Move the PCIe clock-names property from various DTs into SoC dtsi to reduce duplication. In case of a couple of boards, reorder the clock so they match the order in yaml DT bindings. Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: imx8mm: imx8mn: imx8mp: imx8mq: Replace opp-xM with opp-x000000Marek Vasut2022-11-111-3/+3
| | | | | | | | | | | | | | | | | | Fix the following dtbs_check warning on all of i.MX8M variants: " opp-table: Unevaluated properties are not allowed ('opp-25M', 'opp-100M', 'opp-750M' were unexpected) " Using the following command: " $ sed -i '/opp-[0-9]\+M/ s@M {@000000 {@' arch/arm64/boot/dts/freescale/imx8m* " The Documentation/devicetree/bindings/opp/opp-v2-base.yaml expects the OPP subnode names to be full frequency listings in Hz without unit suffixes. Only the i.MX8M DTs are affected per "git grep 'opp-[0-9]\+M'", so fix them. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: imx8m*-venice: add I2C GPIO bus recovery supportTim Harvey2022-10-231-4/+44
| | | | | | | | Add I2C GPIO bus recovery support by adding scl-gpios and sda-gpios for the various I2C busses on Gateworks Venice boards. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: imx: Add i.mx8mm Gateworks gw7904 dts supportTim Harvey2022-09-171-0/+888
The GW7904 is based on the i.MX 8M Mini SoC featuring: - LPDDR4 DRAM - eMMC FLASH - microSD connector with UHS support - LIS2DE12 3-axis accelerometer - Gateworks System Controller - IMX8M FEC - 2x RS232 off-board connectors - PMIC - 10x bi-color LED's - 1x miniPCIe socket with PCIe and USB2.0 - 802.3at Class 4 PoE - 10-30VDC input via barrel-jack Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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