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* arm64: dts: marvell: armada-7040-db: use SPDX-License-IdentifierGregory CLEMENT2018-02-141-40/+1
| | | | | | | | | | | | | | | Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* arm64: dts: marvell: armada-3720-espressobin: use SPDX-License-IdentifierGregory CLEMENT2018-02-141-37/+1
| | | | | | | | | | | | | | Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* arm64: dts: marvell: armada-3720-db: use SPDX-License-IdentifierGregory CLEMENT2018-02-141-38/+1
| | | | | | | | | | | | | | Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* arm64: dts: marvell: use SPDX-License-Identifier for Armada SoCsGregory CLEMENT2018-02-1417-596/+18
| | | | | | | | | | | | | | Follow the recent trend for the license description, and also fix the wrongly stated X11 to MIT. As already pointed on the DT ML, the X11 license text [1] is explicitly for the X Consortium and has a couple of extra clauses. The MIT license text [2] is actually what the current DT files claim. [1] https://spdx.org/licenses/X11.html [2] https://spdx.org/licenses/MIT.html Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* arm64: dts: marvell: mcbin: fix board name typoBaruch Siach2018-02-141-1/+1
| | | | | | | A 'C' was missing in the model name, this patch fixes it. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* arm64: dts: marvell: mcbin: enable uart headersBaruch Siach2018-02-141-0/+22
| | | | | | | | | | | | | Add description of the J25 and J27 UART headers of the Macchiatobin. They use uart peripherals that the CP0 (J25) and CP1 (J27) provide. Even though J25 and J27 are labeled as UART header, the pins on these headers can be muxed for other purposes. But the UART functionality is useful when the board is mounted in an ATX style enclosure, since the console UART is not accessible through the microUSB at CON9. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* arm64: dts: marvell: add CP110 uart peripheralsBaruch Siach2018-02-141-0/+40
| | | | | | | | The CP110 component has 4 uart peripherals. All of them use the same clock gate for slow peripherals that is shared with the i2c and spi peripherals. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* ARM64: dts: marvell: armada-cp110: Add registers clock for I2C nodesGregory CLEMENT2018-02-141-2/+6
| | | | | | | | | | | | This extra clock is needed to access the registers of the I2C controller used on the Armada 7K/8K SoCs. This follows the changes already made in the binding documentation (as well as in the driver) in: commit 1534156e999735fe0befad958e1447600c0c20e7 ("i2c: mv64xxx: Fix clock resource by adding an optional bus clock") Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* ARM64: dts: marvell: armada-cp110: Add registers clock for SPI nodesGregory CLEMENT2018-02-141-2/+6
| | | | | | | | | | | | This extra clock is needed to access the registers of the SPI controller used on Armada 7K/8K SoCs. This follows the changes already made in the binding documentation (as well as in the driver) in: 'commit 92ae112e477ac412decc3fdd5c1eeb6c90c266b4 ("spi: orion: Fix clock resource by adding an optional bus clock")'. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* arm64: dts: marvell: armada-80x0: Fix pinctrl compatible stringGregory CLEMENT2018-01-121-2/+2
| | | | | | | | | | | | | | | When replacing the cpm by cp0 and cps by cp1 [1] not only the label and the alias were replaced but also the compatible string which was wrong. Due to this the pinctrl driver was no more probed. This patch fix it by reverting this change for the pinctrl compatible string on Armada 8K. [1]: "arm64: dts: marvell: replace cpm by cp0, cps by cp1" Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: add Ethernet aliasesYan Markman2018-01-053-0/+19
| | | | | | | | | | | This patch adds Ethernet aliases in the Marvell Armada 7040 DB, 8040 DB and 8040 mcbin device trees so that the bootloader setup the MAC addresses correctly. Signed-off-by: Yan Markman <ymarkman@marvell.com> [Antoine: commit message, small fixes] Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: replace cpm by cp0, cps by cp1Thomas Petazzoni2018-01-057-129/+129
| | | | | | | | | | | | | | | | | In preparation for the introduction of more than 2 CPs in upcoming SoCs, it makes sense to move away from the "CP master" (cpm) and "CP slave" (cps) naming, and use instead cp0/cp1. This commit is the result of: sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/* sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/* So it is a purely mechaninal change. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Suggested-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: de-duplicate CP110 descriptionThomas Petazzoni2018-01-056-904/+508
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One concept of Marvell Armada 7K/8K SoCs is that they are made of HW blocks composed of a variety of IPs (network, PCIe, SATA, XOR, SPI, I2C, etc.), and those HW blocks can be duplicated several times within a given SoC. The Armada 7K SoC has a single CP110 (so no duplication), while the Armada 8K SoC has two CP110. In the future, SoCs with more than 2 CP110s will be introduced. In current kernel versions, the master CP110 is described in armada-cp110-master.dtsi and the slave CP110 is described in armada-cp110-slave.dtsi. Those files are basically exactly the same, since they describe the same hardware. They only have a few differences: - Base address of the registers is different for the "config-space" - Base address of the PCIe registers, MEM, CONF and IO areas were different - Labels (and phandles pointing to them) of the nodes were different ("cpm" prefix in the master CP, "cps" prefix in the slave CP) This duplication issue has been discussed at the DT workshop [1] in Prague last October, and we presented on this topic [2]. The solution of using the C pre-processor to avoid this duplication has been validated by the people present in this DT workshop, and this patch simply implements what has been presented. We handle differences between the master CP and slave CP description using the C pre-processor, by defining a set of macros with different values armada-cp110.dtsi is included to instantiate one of the master or slave CP110. There are a few aspects that deserve additional explanations: - PCIe needs to be handled separately because it is not part of the config-space {...} node, since it has registers outside of the range covered by config-space {...}. - We need to defined CP110_BASE, CP110_PCIEx_BASE without 0x, because they are used for the unit address part of some DT nodes. But since they are also used for the "reg" property of the same nodes, we have an ADDRESSIFY() macro that prepends 0x to those values. We compared the resulting .dtb for armada-8040-db.dtb before and after this patch is applied, and the result is exactly the same, except for a few differences: - the SDHCI controller that was only described in the master CP110 is now also described in the slave CP110. Even though the SDHCI controller from the slave CP110 is indeed not usable (as it isn't wired to the outside world) it is technically part of the silicon, and therefore it is reasonable to also describe it to be part of the slave CP110. In addition, if we wanted to get this correct for the SDHCI controller, we should also do it for the NAND controller, for which the situation is even more complicated: in a single CP110 configuration (Armada 7K), the usable NAND controller is in the master CP110, while in a dual CP110 configuration (Armada 8K), the usable NAND controller is in the slave CP110. Since that would add a lot of additional complexity for no good reason, and since the IP blocks are in fact really present in both CPs, we simply describe them in both CPs at the DT level. - the cp110-master and cp110-slave nodes are now named cpm and cps. We could have kept cp110-master and cp110-slave, but that would have required adding another CP110_xyz define, which didn't seem very useful. Note that this commit also gets rid of the armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, as future SoCs will have more than 2 CPs. Instead, we instantiate the CPs directly from the SoC-specific .dtsi files, i.e armada-70x0.dtsi and armada-80x0.dtsi. [1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad [2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf [gregory.clement@free-electrons.com: add back the "ARM64: dts: marvell: Fix clock resources for various node" commit] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8KThomas Petazzoni2018-01-055-5/+7
| | | | | | | | | | | | | | | | | | | We are currently using the cell-index DT property to assign SPI bus numbers. This property is specific to the spi-orion driver, and requires each SPI controller to have a unique ID defined in the Device Tree. As we are about to merge armada-cp110-master.dtsi and armada-cp110-slave.dtsi into a single file, those cell-index properties that differ between the master CP110 and the slave CP110 are a difference that would have to be handled. In order to avoid this, we switch to using the "aliases" DT node to assign a unique number to each SPI controller. This is more generic, and directly handled by the SPI core. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: use mvebu-icu.h where possibleThomas Petazzoni2018-01-052-2/+2
| | | | | | | | | | | | Back when the ICU Device Tree binding was introduced, we could not use mvebu-icu.h from the Device Tree files, because the DT files and mvebu-icu.h were following different merge routes towards Linus tree. Now that both have been merged, we can switch the Marvell Armada CP110 Device Tree files to use the mvebu-icu.h header instead of duplicating the ICU_GRP_NSR definition. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: fix compatible string list for Armada CP110 slave NANDThomas Petazzoni2018-01-051-2/+2
| | | | | | | | | | The Armada CP110 slave NAND controller Device Tree description lists the compatible string in the wrong order: marvell,armada-8k-nand should come first. This commit alignes the slave CP110 description with the master CP110 description from that respect. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: fix typos in comment describing the NAND controllerThomas Petazzoni2018-01-052-2/+2
| | | | | | | | | Fix the same typo duplicated in both master and slave version of armada-cp110-*.dtsi file: s/limiation/limitation/. [gregory.clement@free-electrons.com: add the commit log] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: use lower case for unit address and reg propertyThomas Petazzoni2018-01-051-2/+2
| | | | | | | | | This fixes the following DTC warning: <stdout>: Warning (simple_bus_reg): Node /ap806/config-space@f0000000/thermal@6f808C simple-bus unit address format error, expected "6f808c" Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: fix watchdog unit address in Armada AP806Thomas Petazzoni2018-01-051-1/+1
| | | | | | | | | This fixes the following DTC warning: Warning (simple_bus_reg): Node /ap806/config-space@f0000000/watchdog@600000 simple-bus unit address format error, expected "610000" Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: armada-37xx: add a crypto nodeAntoine Tenart2018-01-051-0/+14
| | | | | | | | This patch adds a crypto node describing the EIP97 engine found in Armada 37xx SoCs. The cryptographic engine is enabled by default. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* Merge branch 'mvebu/fixes' into HEADGregory CLEMENT2018-01-052-8/+14
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| * ARM64: dts: marvell: armada-cp110: Fix clock resources for various nodeGregory CLEMENT2018-01-052-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the CP modules we found on Armada 7K/8K, many IP block actually also need a "functional" clock (from the bus). This patch add them which allows to fix some issues hanging the kernel: If Ethernet and sdhci driver are built as modules and sdhci was loaded first then the kernel hang. Fixes: bb16ea1742c8 ("mmc: sdhci-xenon: Fix clock resource by adding an optional bus clock") Cc: stable@vger.kernel.org Reported-by: Riku Voipio <riku.voipio@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | ARM64: dts: marvell: Add thermal support for A7K/A8KMiquel Raynal2017-12-183-0/+18
| | | | | | | | | | | | | | | | Add thermal DT nodes in AP806 and CP110 master/slave DTSI files. Suggested-by: David Sniatkiwicz <davidsn@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: armada-37xx: add nodes allowing cpufreq supportGregory CLEMENT2017-12-182-0/+8
| | | | | | | | | | | | | | In order to be able to use cpu freq, we need to associate a clock to each CPU and to expose the power management registers. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: add NAND support on the 8040-DB boardMiquel Raynal2017-12-183-1/+47
|/ | | | | | | | | | | | | Add NAND support on the Armada-8040-DB by adding the same tree as for the Armada-7040-DB by using the same compatible string "marvell,armada-8k-nand". Do not enable the NAND node as enabling it (and changing manually the proper DPR-76 switch) would disable MDIO from CP1 (and thus disable CPS Ethernet PHY). Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2017-11-1615-34/+311
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM device-tree updates from Arnd Bergmann: "We add device tree files for a couple of additional SoCs in various areas: Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for networking, Amlogic A113D for audio, and Renesas R-Car V3M for automotive. As usual, lots of new boards get added based on those and other SoCs: - Actions S500 based CubieBoard6 single-board computer - Amlogic Meson-AXG A113D based development board - Amlogic S912 based Khadas VIM2 single-board computer - Amlogic S912 based Tronsmart Vega S96 set-top-box - Allwinner H5 based NanoPi NEO Plus2 single-board computer - Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers - Allwinner A83T based TBS A711 Tablet - Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8 - Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500 wireless access points and routers - NXP i.MX51 based Zodiac Inflight Innovations RDU1 board - NXP i.MX53 based GE Healthcare PPD biometric monitor - NXP i.MX6 based Pistachio single-board computer - NXP i.MX6 based Vining-2000 automotive diagnostic interface - NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants - Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone - Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet - Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA - Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board - Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards - Renasas r8a7745 based iWave G22D-SODIMM SoM - Rockchip rk3288 based Amarula Vyasa single-board computer - Samsung Exynos5800 based Odroid HC1 single-board computer For existing SoC support, there was a lot of ongoing work, as usual most of that concentrated on the Renesas, Rockchip, OMAP, i.MX, Amlogic and Allwinner platforms, but others were also active. Rob Herring and many others worked on reducing the number of issues that the latest version of 'dtc' now warns about. Unfortunately there is still a lot left to do. A rework of the ARM foundation model introduced several new files for common variations of the model" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (599 commits) arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3 dt-bindings: bus: Add documentation for the Technologic Systems NBUS arm64: dts: actions: s900-bubblegum-96: Add fake uart5 clock ARM: dts: owl-s500: Add CubieBoard6 dt-bindings: arm: actions: Add CubieBoard6 ARM: dts: owl-s500-guitar-bb-rev-b: Add fake uart3 clock ARM: dts: owl-s500: Set power domains for CPU2 and CPU3 arm: dts: mt7623: remove unused compatible string for pio node arm: dts: mt7623: update usb related nodes arm: dts: mt7623: update crypto node ARM: dts: sun8i: a711: Enable USB OTG ARM: dts: sun8i: a711: Add regulator support ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1 ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1 ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes ARM: dts: sunxi: Add dtsi for AXP81x PMIC arm64: dts: allwinner: H5: Restore EMAC changes ...
| * Merge tag 'mvebu-dt64-4.15-2' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann2017-11-073-2/+38
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/dt Pull "mvebu dt64 for 4.15 (part 2)" from Gregory CLEMENT: Add the extended UART support on Armada 3700 * tag 'mvebu-dt64-4.15-2' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: armada-3720-espressobin: fill UART nodes arm64: dts: marvell: armada-3720-db: enable second UART port arm64: dts: marvell: armada-37xx: add second UART port arm64: dts: marvell: armada-37xx: add UART clock
| | * arm64: dts: marvell: armada-3720-espressobin: fill UART nodesMiquel Raynal2017-10-301-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fill ESPRESSObin uart0 node with pinctrl information like in the Armada-3720-DB device tree (which uses the same node). Also explain how to enable the second UART port available on the headers. This second port is not enabled by default because both headers are dedicated to expose general purpose pins and remapping some of them to use the second UART would break existing users. Suggested-by: László ÁSHIN <laszlo@ashin.hu> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: armada-3720-db: enable second UART portMiquel Raynal2017-10-301-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable Armada-3720-DB second UART port by adding the corresponding device tree node in the board DTS and enabling it. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: armada-37xx: add second UART portMiquel Raynal2017-10-301-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a node in Armada 37xx DTSI file for the second UART, with a different compatible due to its extended IP which has some differences with the first UART already in place. Make use of this commit to also fully describe the first port and use the same clear and named interrupt bindings for both ports. The standard UART (UART0) uses level-interrupts while the extended UART (UART1) uses edge-triggered interrupts. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: armada-37xx: add UART clockMiquel Raynal2017-10-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing clock property to armada-3700 UART node. This clock will be used to derive the prescaler value to comply with the requested baudrate. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * | Merge tag 'mvebu-dt64-4.15-1' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann2017-10-309-19/+260
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/dt Pull "mvebu dt64 for 4.15 (part 1)" from Gregory CLEMENT: On Armada 7K/8k: - Improve network support at SoC and board level - Enable watchdog - Add UART muxing - On 7040 DB: add CD SDIO and NAND support - On 8040 DB: add PCIE more ports and SPI1 On Armada 37xx: - Fix UART register size - Add vmmc regulator for SD on 3720 DB * tag 'mvebu-dt64-4.15-1' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: 7040-db: Add the carrier detect pin for SD card on CP arm64: dts: marvell: 7040-db: Document the gpio expander arm64: dts: marvell: enable additional PCIe ports on Armada 8040 DB arm64: dts: marvell: add NAND support on the 7040-DB board arm64: dts: marvell: Enable Armada-8040-DB CPS SPI1 arm64: dts: marvell: 8040-db: enable the SFP ports arm64: dts: marvell: 7040-db: enable the SFP port arm64: dts: marvell: 7040-db: add comphy reference to Ethernet port arm64: dts: marvell: mcbin: add comphy references to Ethernet ports arm64: dts: marvell: 37xx: remove empty line arm64: dts: marvell: cp110: add PPv2 port interrupts arm64: dts: marvell: add comphy nodes on cp110 master and slave arm64: dts: marvell: extend the cp110 syscon register area length arm64: dts: marvell: enable AP806 watchdog arm64: dts: marvell: Fix A37xx UART0 register size arm64: dts: marvell: armada-3720-db: Add vmmc regulator for SD slot arm64: dts: marvell: add UART muxing on Armada 7K/8K
| | * arm64: dts: marvell: 7040-db: Add the carrier detect pin for SD card on CPGregory CLEMENT2017-10-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The SD card slot connected to the SD controller of the CP part has a carrier detect pin connected the gpio expander. This patch enables it allowing supporting the hotplug event for the SD card. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: 7040-db: Document the gpio expanderGregory CLEMENT2017-10-121-0/+10
| | | | | | | | | | | | | | | | | | Document all the GPIO of the expander based on the schematics Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: enable additional PCIe ports on Armada 8040 DBThomas Petazzoni2017-10-021-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada 8040 DB has numerous PCIe ports, so let's enable a few more of those PCIe ports that are enabled in the default bootloader configuration. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: add NAND support on the 7040-DB boardGregory CLEMENT2017-09-274-2/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND controller used in A7K/A8K is present on the CP110 master part. It is compatible with the pxa3xx_nand driver but requires the use of the marvell,armada-8k-nand compatible string due to the need to first enable the NAND controller. Add properties to the NAND node to fit the bindings constraints of the pxa3xx_nand driver and enable the NAND controller. Add the 'marvell,system-controller' property to the cp110 master NAND node with a reference to the syscon node. This is new compared to other boards using the pxa3xx_nand driver and it is needed to be bootloader independent and enable the NAND controller from the NAND controller driver itself by writing in these syscon registers. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> [miquel.raynal@free-electrons.com: add NAND ready/busy MPP subnode, change compatible string to fit the needs of the A7k/A8k SoCs and add the system controller property] Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
| | * arm64: dts: marvell: Enable Armada-8040-DB CPS SPI1Christine Gharzuzi2017-09-251-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the DT node enabling Armada-8040-DB CPS SPI controller driver. Add the SPI NAND flash device connected on the bus. Fill the MTD partitions layout. Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: 8040-db: enable the SFP portsAntoine Tenart2017-09-221-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the SFP ports on the Armada 8040 DB as these ports are now supported by the PPv2 driver (since the PHY is now optional). Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: 7040-db: enable the SFP portAntoine Tenart2017-09-221-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the SFP port on the Armada 7040 DB as this port is now supported by the PPv2 driver (since the PHY is now optional). Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: 7040-db: add comphy reference to Ethernet portAntoine Tenart2017-09-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a comphy phandle to the Ethernet port in the 7040-db device tree. The comphy is used to configure the serdes PHYs used by these ports. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: mcbin: add comphy references to Ethernet portsAntoine Tenart2017-09-221-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds comphy phandles to the Ethernet ports in the mcbin device tree. The comphy is used to configure the serdes PHYs used by these ports. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: 37xx: remove empty lineAntoine Tenart2017-09-201-1/+0
| | | | | | | | | | | | | | | | | | | | | Cosmetic patch removing an empty line at the end of the NB pinctrl node. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: cp110: add PPv2 port interruptsAntoine Tenart2017-09-202-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Ports interrupts are used by the PPv2 driver when no PHY is connected to a port. This patch adds a description of these interrupts. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: add comphy nodes on cp110 master and slaveAntoine Tenart2017-09-202-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch describes the comphy available in the cp110 master and slave. This comphy provides serdes lanes used by various controllers such as the network one. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: extend the cp110 syscon register area lengthAntoine Tenart2017-09-202-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch extends on both cp110 the system register area length to include some of the comphy registers as well. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: enable AP806 watchdogBaruch Siach2017-09-191-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | This watchdog is ARM SBSA generic watchdog. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: Fix A37xx UART0 register sizeallen yan2017-09-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armada-37xx UART0 registers are 0x200 bytes wide. Right next to them are the UART1 registers that should not be declared in this node. Update the example in DT bindings document accordingly. Signed-off-by: allen yan <yanwei@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: armada-3720-db: Add vmmc regulator for SD slotGregory CLEMENT2017-09-191-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By adding this regulator, a proper reset is done during boot. Without this, the UHS failed to be detected after a warm reboot when the SD card remained in the slot, then it fallback to an HS. Note that the vmcc is supported by the xenon driver only with the following fix: "mmc: sdhci-xenon: add set_power callback". Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * arm64: dts: marvell: add UART muxing on Armada 7K/8KThomas Petazzoni2017-09-194-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the relevant details in the Armada 7K/8K Device Tree to properly mux the UART used for the serial console. Since there is basically only one possible muxing for the UART0 on the AP, the muxing configuration is described in armada-ap806.dtsi, and selected from the individual boards (other boards could be using a different UART). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * | arm64: dts: fix unit-address leading 0sRob Herring2017-10-208-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm64/boot/dts -type -f -name '*.dts*' Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 15:48:03 +0000