linux-stable.git - Linux kernel stable tree

	Commit message (Collapse)	Author	Age	Files	Lines
*	arm64: dts: ti: k3-am62a7: Add MIT license along with GPL-2.0	Nishanth Menon	2024-02-06	1	-2/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Modify license to include dual licensing as GPL-2.0-only OR MIT license for SoC and TI evm device tree files. This allows for Linux kernel device tree to be used in other Operating System ecosystems such as Zephyr or FreeBSD. While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated). While at this, update the TI copyright year to sync with current year to indicate license change (and add it at least for one file which was missing TI copyright). Cc: Julien Panis <jpanis@baylibre.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Julien Panis <jpanis@baylibre.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240122145539.194512-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
*	arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KB	Vignesh Raghavendra	2023-03-20	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \|	Per AM62Ax SoC datasheet[0] L2 cache is 512KB. [0] https://www.ti.com/lit/gpn/am62a7 Page 1. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230320044935.2512288-2-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
*	arm64: dts: Update cache properties for ti	Pierre Gondois	2023-01-16	1	-0/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221107155825.1644604-24-pierre.gondois@arm.com
*	arm64: dts: ti: Introduce AM62A7 family of SoCs	Vignesh Raghavendra	2022-09-13	1	-0/+103
	The AM62A SoC belongs to the K3 Multicore SoC architecture platform that can run edge AI applications with Video/Vision processing. This provides advanced system integration with high security support to enable a broad set of applications in industrial/automotive markets such as, driver monitoring, machine vision, smart camera, eMirror, front camera, robotics, and building automation. Some highlights of AM62A SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier accelerator (MMA) for Deep Learning usage. * VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to 315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging and vision image processing. * H.264/H.265 Video Encode/Decode. + Motion JPEG encode * Display support, providing 24-bit RBG parallel interface up to 200MHz pixel clock support for 2K display resolution. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment * One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/zip/spruj16 Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Devarsh Thakkar <devarsht@ti.com> Link: https://lore.kernel.org/r/20220901141328.899100-5-vigneshr@ti.com