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* arm64: dts: ti: k3-j721e: Add MIT license along with GPL-2.0Nishanth Menon2024-02-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify license to include dual licensing as GPL-2.0-only OR MIT license for SoC and TI evm device tree files. This allows for Linux kernel device tree to be used in other Operating System ecosystems such as Zephyr or FreeBSD. While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated). While at this, update the TI copyright year to sync with current year to indicate license change (and add it at least for one file which was missing TI copyright). Cc: "Alexander A. Klimov" <grandmaster@al2klimov.de> Cc: Jerome Neanne <jneanne@baylibre.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240122145539.194512-9-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* arm64: dts: ti: k3-j721e-som-p0: Do not split single itemsAndrew Davis2024-02-051-9/+9
| | | | | | | | | | Each "mboxes" item is composed of two cells. It seems these got split as they appeared to be two items in an array, but are actually a single two-cell item. Rejoin these cells. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20240123222536.875797-10-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* arm64: dts: ti: k3-j721e-som-p0: Add TP6594 family PMICsJerome Neanne2023-12-131-0/+160
| | | | | | | | | | | | | | | | | This patch adds support for TPS6594 PMIC family on wakup I2C0 bus. Theses devices provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Jerome Neanne <jneanne@baylibre.com> Signed-off-by: Esteban Blanc <eblanc@baylibre.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20231208114919.3429562-4-n-francis@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
* arm64: dts: ti: k3-j721e: Enable C6x DSP nodes at the board levelAndrew Davis2023-08-101-0/+2
| | | | | | | | | | | | | | | | | | C6x DSP nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with both mboxes and memory-region information. As theses only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the C6x DSP nodes in the dtsi files and only enable the ones that are given the required mboxes and memory-region on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Acked-by: Hari Nagalla <hnagalla@ti.com> Tested-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230809180145.53158-3-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
* arm64: dts: ti: k3-j721e: Enable C7x DSP nodes at the board levelAndrew Davis2023-08-101-0/+1
| | | | | | | | | | | | | | | | | | C7x DSP nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with both mboxes and memory-region information. As theses only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the C7x DSP nodes in the dtsi files and only enable the ones that are given the required mboxes and memory-region on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Acked-by: Hari Nagalla <hnagalla@ti.com> Tested-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230809180145.53158-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
* arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board levelAndrew Davis2023-08-091-0/+1
| | | | | | | | | | | | | | | | | OSPI nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-6-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
* arm64: dts: ti: k3-j721e-som-p0: Remove Duplicated wkup_i2c0 nodeUdit Kumar2023-07-251-13/+0
| | | | | | | | | | wkup_i2c0 and associated eeprom device node were duplicated, This patch fixes the node duplication. Fixes: 4af0332876f9 ("arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom") Signed-off-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230721082344.1534094-1-u-kumar1@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
* arm64: dts: ti: Unify pin group node names for make dtbs checksTony Lindgren2023-06-151-3/+3
| | | | | | | | | | | | | | | | | | | | Prepare for pinctrl-single yaml binding and unify pin group node names. Let's standardize on pin group node naming ending in -pins. As we don't necessarily have a SoC specific compatible property for pinctrl-single. I'd rather not add a pattern match for pins somewhere in the name for all the users. Trying to add matches for pins-default will be futile as on the earlier SoCs we've already seen names like pins-sleep, pins-idle, pins-off and so on that would need to be matched. And as the node is a pin group, let's prefer to use naming -pins rather than -pin as more pins may need to be added to the pin group later on. Signed-off-by: Tony Lindgren <tony@atomide.com> [vigneshr@ti.com: Rebase onto latest ti/next and extend to new nodes] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eepromNishanth Menon2023-06-151-0/+13
| | | | | | | | | Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eepromNishanth Menon2023-06-151-0/+13
| | | | | | | | | Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* arm64: dts: ti: j721e-som/common-proc-board: Add product linksNishanth Menon2023-06-151-0/+2
| | | | | | | | Add product links to get reference to schematics and design files Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230601183151.1000157-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* arm64: dts: ti: k3-j721e-som-p0/common-proc-board: Fixup reference to ↵Nishanth Menon2023-06-151-9/+9
| | | | | | | | | | | | | phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230606182220.3661956-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* arm64: dts: ti: k3-j721e: Describe OSPI and QSPI flash partition infoVaishnav Achath2023-06-151-0/+46
| | | | | | | | | | | | | | Describe OSPI and QSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. J721E SoM has a MT35 64 MiB OSPI flash and MT25 64 MiB QSPI flash both with sector size of 128 KiB thus the size of the smallest partition is chosen as 128KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20230513141712.27346-2-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash nodeVaishnav Achath2023-06-151-0/+71
| | | | | | | | | | | | J721E SoM has a HyperFlash and HyperRam connected to HyperBus memory controller, add corresponding node, pinmux and partitions for the same. HyperBus is muxed with OSPI and only one controller can be active at a time, therefore keep HyperBus node disabled. Bootloader will detect the external mux state through a wkup gpio and enable the node as required. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20230513123313.11462-3-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* arm64: dts: ti: k3-j721e: Enable Mailbox nodes at the board levelAndrew Davis2022-10-281-28/+5
| | | | | | | | | | | | | | | | | | Mailbox nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221020160305.18711-9-afd@ti.com
* arm64: dts: ti: k3-*: Drop address and size cells from flash nodesPratyush Yadav2022-02-221-2/+0
| | | | | | | | | | | Specifying partitions directly under the flash nodes is deprecated. A partitions node should used instead. The address and size cells are not needed. Remove them. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Apurva Nandan<a-nandan@ti.com> Link: https://lore.kernel.org/r/20220217181025.1815118-2-p.yadav@ti.com
* arm64: dts: ti: k3-*: Fix whitespace around flash@0 nodesPratyush Yadav2022-02-221-1/+1
| | | | | | | | | | The OSPI flash nodes are missing a space before the opening brace. Fix that. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Apurva Nandan<a-nandan@ti.com> Link: https://lore.kernel.org/r/20220217181025.1815118-1-p.yadav@ti.com
* arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPIPratyush Yadav2021-03-111-2/+2
| | | | | | | | | | | | | Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the frequency to 25 MHz. This is the frequency that the flash has been successfully tested with in Octal DTR mode. The total performance should still increase since 8D-8D-8D mode should be at least twice as fast as 1S-1S-8S mode. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20210305153926.3479-2-p.yadav@ti.com
* arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for R5FsSuman Anna2020-11-121-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | Two carveout reserved memory nodes each have been added for each of the R5F remote processor devices within both the MCU and MAIN domains for the TI J721E EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables either to allocate the memory for firmware memory segments. Note that the R5F1 carveouts are needed only if the R5F cluster is running in Split (non-LockStep) mode. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20201029033802.15366-9-s-anna@ti.com
* arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5FsSuman Anna2020-11-121-1/+25
| | | | | | | | | | | | | | | | | | | | | Add the required 'mboxes' property to all the R5F processors for the TI J721E common processor board. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the R5Fs. The nodes are therefore added in the common k3-j721e-som-p0.dtsi file so that all of these can be co-located. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Note that any R5F Core1 resources are needed and used only when that R5F cluster is configured for Split-mode. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20201029033802.15366-8-s-anna@ti.com
* arm64: dts: ti: k3-*: Fix up node_name_chars_strict warningsNishanth Menon2020-09-071-1/+1
| | | | | | | | | | Building with W=2 throws up a bunch of easy to fixup warnings.. node_name_chars_strict is one of them.. Knock those out. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-9-nm@ti.com
* arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS coresSuman Anna2020-08-311-0/+6
| | | | | | | | | | | | | Add a reserved memory node to reserve a portion of the DDR memory to be used for performing inter-processor communication between all the remote processors running RTOS on the TI J721E EVM boards. 28 MB of memory is reserved for this purpose, and this accounts for all the vrings and vring buffers between all the possible pairs of remote processors. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20200825172145.13186-9-s-anna@ti.com
* arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C71x DSPSuman Anna2020-08-311-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Two carveout reserved memory nodes have been added for the lone C71x DSP remote processor device present within the MAIN voltage domain for the TI J721E EVM boards. These nodes are assigned to the respective rproc device node as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The C71x DSP processor does support a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. The firmware images currently do not need any RSC_CARVEOUT entries either in their resource tables to allocate the memory for firmware memory segments. The reserved memory nodes can be disabled later on if there is no use-case defined to use the C71x DSP remoteproc processor. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20200825172145.13186-8-s-anna@ti.com
* arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C71x DSPSuman Anna2020-08-311-0/+4
| | | | | | | | | | | | | | | | | | Add the required 'mboxes' property to the C71x DSP processor for the TI J721E common processor board. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the DSPs. The nodes are therefore added in the common k3-j721e-som-p0.dtsi file so that all of these can be co-located. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20200825172145.13186-7-s-anna@ti.com
* arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPsSuman Anna2020-08-311-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Two carveout reserved memory nodes each have been added for each of the C66x DSP remote processor devices present within the MAIN voltage domain for the TI J721E EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc devices, and the second region will furnish the static carveout regions for the firmware memory. The minimum granularity on the Cache settings on C66x DSP cores is 16 MB, so the DMA memory regions are chosen such that they are in separate 16 MB regions for each DSP, while reserving a total of 16 MB for each DSP and not changing the overall DSP remoteproc carveouts. The current carveout addresses and sizes are defined statically for each device. The C66x DSP processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables to allocate the memory for firmware memory segments. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20200825172145.13186-5-s-anna@ti.com
* arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to C66x DSPsSuman Anna2020-08-311-0/+8
| | | | | | | | | | | | | | | | | | Add the required 'mboxes' property to both the C66x DSP processors for the TI J721E common processor board. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the DSPs. The nodes are therefore added in the common k3-j721e-som-p0.dtsi file so that all of these can be co-located. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20200825172145.13186-4-s-anna@ti.com
* arm64: dts: ti: k3-j721e-som-p0: Move mailbox nodes from board dts fileSuman Anna2020-08-311-0/+93
| | | | | | | | | | | | | | | The commit eb9f9173d01f ("arm64: dts: ti: k3-j721e-common-proc-board: Add IPC sub-mailbox nodes") has added the sub-mailbox nodes used by various remote processors and disabled the unused mailbox clusters directly in the k3-j721e-common-proc-board dts file. Move all of these nodes into the k3-j721e-som-p0.dtsi file instead to co-locate all the mailboxes and the soon to be added DDR reserved-memory carveout nodes used by remoteprocs within the same dtsi file. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20200825172145.13186-2-s-anna@ti.com
* arm64: dts: ti: k3-*: Replace HTTP links with HTTPS onesAlexander A. Klimov2020-07-171-1/+1
| | | | | | | | | | | | | | | | | | | | Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* arm64: dts: ti: k3-j721e: Add DT nodes for few peripherialsVignesh Raghavendra2020-01-171-0/+45
| | | | | | | Enable I2Cs, ADCs, OSPIs and UFS peripherals present on J721e. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* arm64: dts: ti: Add support for J721E Common Processor BoardNishanth Menon2019-06-191-0/+29
Add Support for J721E Common Processor board support. The EVM architecture is as follows: +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that has most of the actual connectors, power supply etc. A SOM (System on Module) is plugged on to the common processor board and this contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Add-n card options add further functionality (such as additional Audio, Display, networking options). Note: A) The minimum configuration required to boot up the board is System On Module(SOM) + Common Processor Board. B) Since there is just a single SOM and Common Processor Board, we are maintaining common processor board as the base dts and SOM as the dtsi that we include. In the future as more SOM's appear, we should move common processor board as a dtsi and include configurations as dts. C) All daughter cards beyond the basic boards shall be maintained as overlays. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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