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* arm64: dts: ti: k3-j7200: fix main pinmux rangeMatt Ranostay2022-09-212-5/+16
| | | | | | | | | | | | | | | Range size of 0x2b4 was incorrect since there isn't 173 configurable pins for muxing. Additionally there is a non-addressable region in the mapping which requires splitting into two ranges. main_pmx0 -> 67 pins main_pmx1 -> 3 pins Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20220919205723.8342-1-mranostay@ti.com
* arm64: dts: ti: Add support for AM62A7-SKVignesh Raghavendra2022-09-132-0/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM62A StarterKit (SK) board is a low cost, small form factor board designed for TI’s AM62A7 SoC. It supports the following interfaces: * 2 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 HDMI Port with audio * x1 Headphone Jack * x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port * x1 UHS-1 capable µSD card slot * M.2 SDIO Wifi + UART slot * 1Gb OSPI NAND flash * x4 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 20-pin header for Programmable Realtime Unit (PRU) IO pins * 40-pin CSI header Add basic support for AM62A7-SK. Schematics: https://www.ti.com/lit/zip/sprr459 Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Devarsh Thakkar <devarsht@ti.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220901141328.899100-6-vigneshr@ti.com
* arm64: dts: ti: Introduce AM62A7 family of SoCsVignesh Raghavendra2022-09-135-0/+616
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM62A SoC belongs to the K3 Multicore SoC architecture platform that can run edge AI applications with Video/Vision processing. This provides advanced system integration with high security support to enable a broad set of applications in industrial/automotive markets such as, driver monitoring, machine vision, smart camera, eMirror, front camera, robotics, and building automation. Some highlights of AM62A SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier accelerator (MMA) for Deep Learning usage. * VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to 315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging and vision image processing. * H.264/H.265 Video Encode/Decode. + Motion JPEG encode * Display support, providing 24-bit RBG parallel interface up to 200MHz pixel clock support for 2K display resolution. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment * One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/zip/spruj16 Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Devarsh Thakkar <devarsht@ti.com> Link: https://lore.kernel.org/r/20220901141328.899100-5-vigneshr@ti.com
* arm64: dts: ti: k3-am625-sk: Add epwm nodesGeorgi Vlaev2022-09-091-0/+12
| | | | | | | | | Add epwm nodes and mark them disabled, as they're not currently in use. Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20220531205229.198011-3-g-vlaev@ti.com
* arm64: dts: ti: k3-am62-main: Add epwm nodesGeorgi Vlaev2022-09-091-0/+33
| | | | | | | | | | | | | Add the compatible DT nodes for all EPWM instances present in AM62 SoC. There is a total of 3 EPWM modules available, sharing the same K3 IP as in AM64 SoC. This also adds a required "ti,am62-epwm-tbclk" clock provider node for the EPWM time-base clock. Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20220531205229.198011-2-g-vlaev@ti.com
* arm64: dts: ti: k3-am642-sk: Add DT entry for onboard LEDsAparna M2022-09-011-0/+77
| | | | | | | | | | AM642 SK has 8 leds connected to tpic2810 onboard. Add support for these gpio leds. Signed-off-by: Aparna M <a-m1@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220830123254.522222-1-vigneshr@ti.com
* arm64: dts: ti: k3-j7200-mcu-wakeup: Add SA2UL nodeAndrew Davis2022-09-011-0/+20
| | | | | | | | | | | | | | | | | | J7200 has an instance of SA2UL in the MCU domain. Add DT node for the same. The device is marked TI_SCI_PD_SHARED as parts of this IP are also shared with the security co-processor and OP-TEE. The RNG node is added but marked disabled as it is firewalled off for exclusive use by OP-TEE. Any access to this device from Linux will result in firewall errors. We add the node for completeness of the hardware description. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20220823001136.10944-4-afd@ti.com
* arm64: dts: ti: k3-am65-main: Do not exclusively claim SA2ULAndrew Davis2022-09-011-1/+1
| | | | | | | | | | | The SA2UL hardware is also used by SYSFW and OP-TEE. It should be requested using the shared TI-SCI flags instead of the exclusive flags or the request will fail. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20220823001136.10944-3-afd@ti.com
* arm64: dts: ti: k3-am65-main: Move SA2UL to unused PSI-L thread IDAndrew Davis2022-09-011-2/+2
| | | | | | | | | | | The first TX and first two RX PSI-L threads for SA2UL are used by SYSFW on High Security(HS) devices. Use the next available threads to prevent resource allocation conflicts. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20220823001136.10944-2-afd@ti.com
* arm64: dts: ti: k3-am65-main: Disable RNG nodeAndrew Davis2022-09-011-0/+1
| | | | | | | | | | | | | | | The hardware random number generator is used by OP-TEE and is access is denied to other users with SoC level bus firewalls. Any access to this device from Linux will result in firewall errors. We could remove this node, but it is still valid device description, and it is possible it could be re-enabled in the bootloader if OP-TEE is not used. So only disable this node for now. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20220823001136.10944-1-afd@ti.com
* arm64: dts: ti: k3-j7200-main: Add main domain watchdog entriesGowtham Tammana2022-09-011-0/+18
| | | | | | | | | Add DT entries for main domain watchdog instances. Signed-off-by: Gowtham Tammana <g-tammana@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20220822235006.7081-1-afd%40ti.com
* arm64: dts: ti: k3-am64-main: Add ELM (Error Location Module) nodeRoger Quadros2022-09-013-0/+17
| | | | | | | | | | | | | The ELM module is used for GPMC NAND accesses for detecting and correcting errors during reads due to NAND bitflips errors. 4-, 8-, and 16-bit error-correction levels are supported using the BCH (Bose-ChaudhurI-Hocquenghem) algorithm. Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220802104456.11069-3-rogerq@kernel.org
* arm64: dts: ti: k3-am64-main: Add GPMC memory controller nodeRoger Quadros2022-09-013-0/+27
| | | | | | | | | | | | | | | The GPMC is a unified memory controller dedicated for interfacing with external memory devices like - Asynchronous SRAM-like memories and ASICs - Asynchronous, synchronous, and page mode burst NOR flash - NAND flash - Pseudo-SRAM devices Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220802104456.11069-2-rogerq@kernel.org
* arm64: dts: ti: k3-j721e-main: fix RNG node clock idDaniel Parks2022-09-011-1/+1
| | | | | | | | | | | | The RNG node for this platform claims pka_in_clk. Change it to claim the correct clock x1_clk. [1] [1]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721e/clocks.html#clocks-for-sa2-ul0-device Signed-off-by: Daniel Parks <danielrparks@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/f29e2c65dc7310a926af8a676651592afac04b03.1659981162.git.danielrparks@ti.com
* arm64: dts: ti: k3-am64-main: Enable crypto acceleratorPeter Ujfalusi2022-09-011-0/+20
| | | | | | | | | | | | | Add the node for SA2UL. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> [s-anna@ti.com: drop label, minor cleanups] Signed-off-by: Suman Anna <s-anna@ti.com> [j-choudhary@ti.com: disable rng-node, change flag to shared] Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20220711085743.10128-3-j-choudhary@ti.com
* arm64: dts: ti: k3-am64: Add SA2UL address space to Main CBASS rangesSuman Anna2022-09-011-0/+1
| | | | | | | | | | | | | Add the address space for the SA2UL in MAIN domain to the ranges property of the cbass_main interconnect node so that the addresses within the corresponding sram nodes and its children can be translated properly by the relevant OF address API. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20220711085743.10128-2-j-choudhary@ti.com
* arm64: dts: ti: k3-am64-main: Add main_cpts labelChristian Gmeiner2022-09-011-1/+1
| | | | | | | | Makes it easier to reference the node in board dts files. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20220822095943.18563-1-christian.gmeiner@gmail.com
* arm64: dts: ti: k3-am62-main: Enable crypto acceleratorJayesh Choudhary2022-07-061-0/+13
| | | | | | | | Add the node for sa3ul crypto accelerator. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220624043905.129207-1-j-choudhary@ti.com
* arm64: dts: ti: k3-am625-sk: Enable ramoopsGuillaume La Roque2022-07-061-0/+9
| | | | | | | | | Enable ramoops features to easily debug some issues. Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220517122828.2985179-1-glaroque@baylibre.com
* arm64: dts: ti: k3-am642-sk: Add pinmux corresponding to main_uart0Aswath Govindraju2022-07-061-0/+14
| | | | | | | | Add pinmux details required for the zeroth instance of main UART. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220516113417.3516-1-a-govindraju@ti.com
* arm64: dts: ti: Align gpio-key node names with dtschemaKrzysztof Kozlowski2022-06-172-4/+4
| | | | | | | | | The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220616005333.18491-29-krzysztof.kozlowski@linaro.org
* arm64: dts: ti: Adjust whitespace around '='Krzysztof Kozlowski2022-06-1713-28/+28
| | | | | | | | | | Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220526204139.831895-1-krzysztof.kozlowski@linaro.org
* arm64: dts: ti: k3-am64-main: Remove support for HS400 speed modeAswath Govindraju2022-06-171-2/+0
| | | | | | | | | | | | | AM64 SoC, does not support HS400 and HS200 is the maximum supported speed mode[1]. Therefore, fix the device tree node to reflect the same. [1] - https://www.ti.com/lit/ds/symlink/am6442.pdf (SPRSP56C – JANUARY 2021 – REVISED FEBRUARY 2022) Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220512064859.32059-1-a-govindraju@ti.com
* arm64: dts: ti: k3-j721s2: Fix overlapping GICD memory regionMatt Ranostay2022-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | GICD region was overlapping with GICR causing the latter to not map successfully, and in turn the gic-v3 driver would fail to initialize. This issue was hidden till commit 2b2cd74a06c3 ("irqchip/gic-v3: Claim iomem resources") replaced of_iomap() calls with of_io_request_and_map() that internally called request_mem_region(). Respective console output before this patchset: [ 0.000000] GICv3: /bus@100000/interrupt-controller@1800000: couldn't map region 0 Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Cc: linux-stable@vger.kernel.org Cc: Marc Zyngier <maz@kernel.org> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220617151304.446607-1-mranostay@ti.com
* arm64: dts: ti: k3-j721e-sk: Enable HDMIRahul T R2022-05-051-1/+79
| | | | | | | | | | | | | Add node for dvi bridge and the endpoint nodes to describe connection from DSS => TI TFP410 DPI-to-DVI Bridge => HDMI connector. Also add the required pinmux for HDMI hotplug and powerdown Signed-off-by: Rahul T R <r-ravikumar@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20220505090709.9252-3-r-ravikumar@ti.com
* arm64: dts: ti: k3-j721e-sk: Enable DisplayPortRahul T R2022-05-051-4/+41
| | | | | | | | | | Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Signed-off-by: Rahul T R <r-ravikumar@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20220505090709.9252-2-r-ravikumar@ti.com
* arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evmTomi Valkeinen2022-05-051-4/+57
| | | | | | | | | | | | Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Also add the required pinmux nodes for hotplug. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Rahul T R <r-ravikumar@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20220429112639.13004-3-r-ravikumar@ti.com
* arm64: dts: ti: k3-j721e-*: add DP & DP PHYTomi Valkeinen2022-05-053-2/+105
| | | | | | | | | | | | | | | | Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. Also add the required phy link nodes in the board dts files. A slight irregularity in the bindings is the DPTX PHY register block, which is in the MHDP IP, but is needed and mapped by the PHY. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Rahul T R <r-ravikumar@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com> Link: https://lore.kernel.org/r/20220429112639.13004-2-r-ravikumar@ti.com
* arm64: dts: ti: k3-am62: Add SA3UL ranges in cbass_mainJayesh Choudhary2022-04-291-0/+1
| | | | | | | | | | Add the address space for SA3UL to the ranges property of the cbass_main node. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220412075008.10553-1-j-choudhary@ti.com
* arm64: dts: ti: k3-am62: Add support for MCANAswath Govindraju2022-04-272-0/+18
| | | | | | | | | | | | AM62 SoC has one instance of MCAN in main domain. However, its corresponding CAN signals are not brought out through a transceiver, on the SK board. Therefore, add the device tree node in the main dt file and set the status to disabled in the SK board dts file. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220418115802.5672-1-a-govindraju@ti.com
* arm64: dts: ti: k3-am62-mcu: Enable MCU GPIO moduleVignesh Raghavendra2022-04-271-0/+28
| | | | | | | | | AM62 has x1 GPIO module and associated interrupt router in MCU Domain. Add DT nodes for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20220421061938.122317-1-vigneshr@ti.com
* arm64: dts: ti: k3-am625-sk: Add ECAP APWM nodesVignesh Raghavendra2022-04-272-0/+39
| | | | | | | | | | AM62 has 3 ECAP instances with 1 APWM each. Add DT nodes for the same. Keep them disabled in am625-sk dts as these pins can be repurposed in user exp connector. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20220419062902.196526-1-vigneshr@ti.com
* arm64: dts: ti: k3-am625-sk: Enable on board peripheralsVignesh Raghavendra2022-04-271-0/+273
| | | | | | | | | Add nodes for I2C IO expander, OSPI Flash, Eth PHYs, SD and eMMC that are present on AM625 SK board. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220427072954.8821-3-vigneshr@ti.com
* arm64: dts: ti: k3-am62: Add more peripheral nodesVignesh Raghavendra2022-04-272-0/+286
| | | | | | | | Add nodes for McSPI, OSPI, DMA, CPSW, MMC and On Chip SRAM nodes. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220427072954.8821-2-vigneshr@ti.com
* arm64: dts: ti: k3-am642-sk: Enable WLAN connected to SDHCI0Kishon Vijay Abraham I2022-04-271-0/+62
| | | | | | | | | | | | WL1837 module is connected to SDHCI0 in AM642 SK. Enable it here. This will enable the WiFi functionaliy on the board. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Aparna M <a-m1@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220414133612.13365-1-a-m1@ti.com
* arm64: dts: ti: k3-am64-mcu: remove incorrect UART base clock ratesMatthias Schiffer2022-04-271-2/+0
| | | | | | | | | | | | | | | | We found that (at least some versions of) the sci-fw set the base clock rate for UARTs in the MCU domain to 96 MHz instead of the expected 48 MHz, leading to incorrect baud rates when used from Linux. As the 8250_omap driver will query the actual clock rate from the clk driver when clock-frequency is unset, removing the incorrect property is sufficient to fix the baud rate. Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20220419075157.189347-1-matthias.schiffer@ew.tq-group.com
* arm64: dts: ti: Add support for AM62-SKNishanth Menon2022-02-282-0/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM62 StarterKit (SK) board is a low cost, small form factor board designed for TI’s AM625 SoC. It supports the following interfaces: * 2 GB DDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode * x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display * x1 Headphone Jack * x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port * x1 UHS-1 capable µSD card slot * 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837 * 512 Mbit OSPI flash * x4 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 20-pin header for Programmable Realtime Unit (PRU) IO pins * 15-pin CSI header Add basic support for AM62-SK. Schematics: https://www.ti.com/lit/zip/sprr448 Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220225120239.1303821-6-vigneshr@ti.com
* arm64: dts: ti: Introduce base support for AM62x SoCVignesh Raghavendra2022-02-285-0/+552
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This add bare minimum DT for AM62 describing ARM compute clusters, Main, MCU and Wakeup domain and interconnects, UARTs and I2Cs to enable booting using ramdisk. Hierarchy of dts files: am62.dtsi: base SoC skeleton which is common across am62xx family of SoCs, includes am62-main.dtsi, am62-mcu.dtsi and am62-wakeup.dtsi representing 3 domains and peripherals in each of these domain am625.dtsi: describes CPU cluster (Quad A53s). Since, am625 is a current superset device with all peripherals, am625.dtsi includes am62.dtsi completing SoC definition. Individual EVMs using this SoC will just need to include am625.dtsi thus making things easier for Board and SOM Vendors. Future derivative SoCs will have their own am62{1-9}{1-9}.dtsi overriding cluster / peripheral definitions with their own compatibles. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruiv7 Co-developed-by: Suman Anna <s-anna@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Co-developed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220225120239.1303821-5-vigneshr@ti.com
* arm64: dts: ti: k3-*: Drop address and size cells from flash nodesPratyush Yadav2022-02-226-12/+0
| | | | | | | | | | | Specifying partitions directly under the flash nodes is deprecated. A partitions node should used instead. The address and size cells are not needed. Remove them. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Apurva Nandan<a-nandan@ti.com> Link: https://lore.kernel.org/r/20220217181025.1815118-2-p.yadav@ti.com
* arm64: dts: ti: k3-*: Fix whitespace around flash@0 nodesPratyush Yadav2022-02-225-5/+5
| | | | | | | | | | The OSPI flash nodes are missing a space before the opening brace. Fix that. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Apurva Nandan<a-nandan@ti.com> Link: https://lore.kernel.org/r/20220217181025.1815118-1-p.yadav@ti.com
* arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regsNishanth Menon2022-02-222-1/+5
| | | | | | | | | | | | | | | | | | | | | | | Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-6-nm@ti.com
* arm64: dts: ti: k3-am64: Fix gic-v3 compatible regsNishanth Menon2022-02-222-1/+5
| | | | | | | | | | | | | | | | | | | | | | | Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A53 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map Cc: stable@vger.kernel.org Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-5-nm@ti.com
* arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regsNishanth Menon2022-02-222-1/+5
| | | | | | | | | | | | | | | | | | | | | | | Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-4-nm@ti.com
* arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regsNishanth Menon2022-02-222-1/+5
| | | | | | | | | | | | | | | | | | | | | | | Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org # 5.10+ Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-3-nm@ti.com
* arm64: dts: ti: k3-am65: Fix gic-v3 compatible regsNishanth Menon2022-02-222-1/+5
| | | | | | | | | | | | | | | | | | | | | | | Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A53 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map Cc: stable@vger.kernel.org # 5.10+ Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-2-nm@ti.com
* arm64: dts: ti: k3-j721s2-mcu-wakeup: Fix the interrupt-parent for ↵Keerthy2022-02-221-2/+2
| | | | | | | | | | | | | | wkup_gpioX instances The interrupt-parent for wkup_gpioX instances are wrongly assigned as main_gpio_intr instead of wkup_gpio_intr. Fix it. Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20220203132647.11314-1-a-govindraju@ti.com
* arm64: dts: ti: k3-am64: Add ESM0 to device memory mapHari Nagalla2022-02-161-0/+1
| | | | | | | | | | | | | | | | | AM64x SoCs have two ESM modules, with one in MAIN voltage domain and the other in MCU voltage domain. The error output from Main ESM module can be routed to the MCU ESM module. The error output of MCU ESM can be configured to reset the device. The MCU ESM configuration address space is already opened and this patch opens the MAIN ESM configuration address space. For ESM details please refer technical reference manual at https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Link: https://lore.kernel.org/r/20220210172246.27871-1-hnagalla@ti.com
* arm64: dts: ti: k3-am65*: Remove #address-cells/#size-cells from flash nodesMatthias Schiffer2022-02-162-8/+2
| | | | | | | | | | | Specifying partitions directly in the flash node is deprecated, a fixed-partitions node should be used instead. Therefore, it doesn't make sense to have these properties in the flash nodes. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20220203140240.973690-2-matthias.schiffer@ew.tq-group.com
* arm64: dts: ti: k3-am64-main: Add RTI watchdog nodesChristian Gmeiner2022-02-042-0/+20
| | | | | | | | | | | Add the needed bus mappings for the two main RTI memory ranges and the required device tree nodes in the main domain. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-By: Hari Nagalla <hnagalla@ti.com> Link: https://lore.kernel.org/r/20220111134552.800704-1-christian.gmeiner@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
* arm64: dts: ti: k3-j721s2-common-proc-board: Alias console uart to serial2Aswath Govindraju2022-01-241-3/+3
| | | | | | | | | | | | On J721s2 Linux console is on main_uart8 but to be consistent with other J7 family of devices, alias it to ttyS2 (serial2). This also eliminates need to have higher number of 8250 runtime UARTs. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20211223121650.26868-3-vigneshr@ti.com
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